Altera Low Latency Ethernet 10G MAC Manuel d'utilisateur Page 99
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GMII RX Signals
Table 5-14: GMII RX Signals
Signal Direction Width Description
gmii_rx_clk In 1 125-MHz RX clock.
gmii_rx_d[] In 8 RX data.
gmii_rx_dv In 1 When asserted, indicates the RX data is valid.
gmii_rx_err In 1 When asserted, indicates the RX data contains
error.
MII TX Signals
The signals below are present in the 10M/100B/1G/10G operating mode.
Table 5-15: MII TX Signals
Signal Direction Width Description
tx_clkena In 1 Clock enable from the PHY IP. This clock
effectively divides gmii_tx_clk to 25 MHz for 100
Mbps and 2.5 MHz for 10 Mbps.
tx_clkena_half_rate In 1 Clock enable from the PHY IP. This clock
effectively divides gmii_tx_clk to 12.5 MHz for
100 Mbps and 1.25 MHz for 10 Mbps.
mii_tx_d[] Out 4 TX data bus.
mii_tx_en Out 1 When asserted, indicates the TX data is valid.
mii_tx_err Out 1 When asserted, indicates the TX data contains
error.
MII RX Signals
The signals below are present in the 10M/100B/1G/10G operating mode.
Table 5-16: MII RX Signals
Signal Direction Width Description
rx_clkena In 1 Clock enable from the PHY IP for 100 Mbps and 10
Mbps operations. This clock effectively divides
gmii_rx_clk to 25 MHz for 100 Mbps and 2.5
MHz for 10 Mbps.
rx_clkena_half_rate In 1 Clock enable from the PHY IP for 100 Mbps and 10
Mbps operations. This clock effectively runs at half
the rate of rx_clkena and divides gmii_rx_clk to
12.5 MHz for 100 Mbps and 1.25 MHz for 10 Mbps.
The rising edges of this signal and rx_clkena must
align.
UG-01144
2014.12.15
GMII RX Signals
5-17
Interface Signals for LL Ethernet 10G MAC
Altera Corporation
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- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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