Altera Low Latency Ethernet 10G MAC Manuel d'utilisateur Page 98
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- Table des matières
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Noté. / 5. Basé sur avis des utilisateurs
Signal Condition Direction Width Description
xgmii_rx_valid
Use legacy Ethernet
10G MAC XGMII
interface disabled.
Enable 10GBASE-R
register mode
enabled.
In 1 When asserted, indicates that the data
and control buses are valid.
xgmii_rx[] Use legacy Ethernet
10G MAC XGMII
interface enabled.
In 72
8-lane SDR XGMII receive data and
control bus. Each lane contains 8 data
plus 1 control bits. The signal mapping
is compatible with the 64-bit MAC.
• Lane 0 data: xgmii_rx[7:0]
• Lane 0 control: xgmii_rx[8]
• Lane 1 data: xgmii_rx[16:9]
• Lane 1 control: xgmii_rx[17]
• Lane 2 data: xgmii_rx[25:18]
• Lane 2 control: xgmii_rx[26]
• Lane 3 data: xgmii_rx[34:27]
• Lane 3 control: xgmii_rx[35]
• Lane 4 data: xgmii_rx[43:36]
• Lane 4 control: xgmii_rx[44]
• Lane 5 data: xgmii_rx[52:45]
• Lane 5 control: xgmii_rx[53]
• Lane 6 data: xgmii_rx[61:54]
• Lane 6 control: xgmii_rx[62]
• Lane 7 data: xgmii_rx[70:63]
• Lane 7 control: xgmii_rx[71]
link_fault_
status_xgmii_
rx_data[]
— Out 2 The following values indicate the link
fault status:
• 0x0 = No link fault
• 0x1 = Local fault
• 0x2 = Remote fault
GMII TX Signals
Table 5-13: GMII TX Signals
Signal Direction Width Description
gmii_tx_clk In 1 125-MHz TX clock.
gmii_tx_d [] Out 8 TX data.
gmii_tx_en Out 2 When asserted, indicates the TX data is valid.
gmii_tx_err Out 2 When asserted, indicates the TX data contains
error.
5-16
GMII TX Signals
UG-01144
2014.12.15
Altera Corporation
Interface Signals for LL Ethernet 10G MAC
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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