Altera Low Latency Ethernet 10G MAC Manuel d'utilisateur Page 19
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Figure 2-5: Upgrading IP Cores
Double-click to
upgrade in editor
(no auto upgrade)
Upgrade required
Migration details
Supports Auto
upgrade
Upgrade success
1. Click File > Open Project and open the Quartus II project containing IP for migration to another
device in the original version of the Quartus II software.
2. To specify a different target device for migration, click Assignments > Device and select the target
device family.
3. To display IP cores requiring migration, click Project > Upgrade IP Components. The Description
field prompts you to run auto update or double-click IP cores for migration.
4. To migrate one or more IP cores that support automatic upgrade, ensure that the Auto Upgrade
option is turned on for the IP core(s), and then click Perform Automatic Upgrade. The Status and
Version columns update when upgrade is complete.
5. To migrate an IP core that does not support automatic upgrade, double-click the IP core name, and
then click OK. The parameter editor appears.
a. If the parameter editor specifies a Currently selected device family, turn off Match project/
default, and then select the new target device family.
b. Click Finish to migrate the IP variation using best-effort mapping to new parameters and settings.
A new parameter editor opens displaying best-effort mapped parameters.
c. Click Generate HDL, and then confirm the Synthesis and Simulation file options. Verilog HDL is
the defauilt output file format specified. If your original IP core was generated for VHDL, select
VHDL to retain the original output format.
2-10
Migrating IP Cores to a Different Device
UG-01144
2014.12.15
Altera Corporation
Getting Started with LL Ethernet 10G MAC
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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