Altera Low Latency Ethernet 10G MAC Manuel d'utilisateur Page 105
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Noté. / 5. Basé sur avis des utilisateurs
Signal Direction Width Description
tx_etstamp_ins_ctrl_offset_
checksum_field[]
In 16 The location of the checksum field,
relative to the first byte of the packet.
Assert this signal in the same clock
cycle as the start of packet (avalon_
st_tx_startofpacket is asserted).
tx_etstamp_ins_ctrl_offset_
checksum_correction[]
In 16 The location of the checksum
correction field, relative to the first
byte of the packet. Assert this signal
in the same clock cycle as the start of
packet (avalon_st_tx_startofpacket is
asserted).
IEEE 1588v2 Ingress Receive Signals
The signals below are present when you select the Enable time stamping option.
Table 5-19: IEEE 1588v2 Ingress Receive Signals
Signal Direction Width Description
rx_ingress_timestamp_96b_valid Out 1 When asserted, this signal qualifies
the timestamp on rx_ingress_
timestamp_96b_data[]. The MAC
IP core asserts this signal in the same
clock cycle it asserts avalon_st_rx_
startofpacket.
rx_ingress_timestamp_96b_data[] Out 96 Carries the 96-bit ingress timestamp
in the following format:
• Bits 48 to 95: 48-bit seconds field
• Bits 16 to 47: 32-bit nanoseconds
field
• Bits 0 to 15: 16-bit fractional
nanoseconds field
The 96-bit timestamp is usually for
noting the complete ToD and is
useful in ordinary clock and
boundary clock devices. The
transparent clock typically uses 64-bit
timestamp.
rx_ingress_timestamp_64b_valid
Out 1 When asserted, this signal qualifies
the timestamp on rx_ingress_
timestamp_64b_data[]. The MAC
IP core asserts this signal in the same
clock cycle it asserts avalon_st_rx_
startofpacket.
UG-01144
2014.12.15
IEEE 1588v2 Ingress Receive Signals
5-23
Interface Signals for LL Ethernet 10G MAC
Altera Corporation
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- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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