Altera Low Latency Ethernet 10G MAC Manuel d'utilisateur Page 61
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Word
Offset
Register Name Description Access HW Reset
Value
0x002D tx_vlan_detection
• Bit 0—TX VLAN detection disable.
0: The MAC detects VLAN and stacked
VLAN frames.
1: The MAC does not detect VLAN and
stacked VLAN frames. When received, the
MAC treats them as basic frames and
considers their tags as payload bytes.
• Bits 31:1—reserved.
RW 0x0
0x002E tx_ipg_10g
• Bit 0—use this bit to specify the average
IPG for operating speed of 10 Gbps.
0: Sets the average IPG to 8 bytes.
1: Sets the average IPG to 12 bytes.
• Bits 31:1—reserved.
The Unidirectional feature does not support
an average IPG of 8 bytes.
RW 0x0
0x002F tx_ipg_10M_100M_1G
• Bits 3:0—use these bits to specify the
average IPG for operating speed of 10
Mbps, 100 Mbps or 1 Gbps. Valid values
are between 8 to 15 bytes.
• Bits 31:4—reserved.
RW 0x0
0x003E tx_underflow_counter0
36-bit error counter that collects the number
of truncated TX frames when TX buffer
underflow persists.
• tx_underflow_counter0: Lower 32 bits of
the error counter.
• tx_underflow_counter1[3:0]: Upper 4
bits of the error counter.
• tx_underflow_counter1[31:4]—
reserved.
To read the counter, read the lower 32 bits
followed by the upper 4 bits. The IP core
clears the counter after a read.
RO 0x0
0x003F tx_underflow_counter1
UG-01144
2014.12.15
TX_Configuration and Status Registers
4-9
Configuration Registers for LL Ethernet 10G MAC
Altera Corporation
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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