Altera Low Latency Ethernet 10G MAC Manuel d'utilisateur Page 100
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- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Signal Direction Width Description
mii_rx_d[] Out 4 RX data bus.
mii_rx_dv Out 1 When asserted, indicates the RX data is valid.
mii_rx_err Out 1 When asserted, indicates the RX data contains
error.
1588v2 Interfaces
IEEE 1588v2 Egress Transmit Signals
The signals below are present when you select the Enable time stamping option.
Table 5-17: IEEE 1588v2 Egress Transmit Signals
Signal Direction Width Description
tx_egress_timestamp_request_
valid
In 1 Assert this signal to request for a
timestamp for the transmit frame.
This signal must be asserted in the
same clock cycle avalon_st_tx_
startofpacket is asserted.
tx_egress_timestamp_request_
fingerprint[]
In n n = value of the Timestamp
fingerprint width parameter.
Use this bus to specify the fingerprint
of the transmit frame that you are
requesting a timestamp for. This bus
must carry a valid fingerprint at the
same time tx_egress_timestamp_
request_valid is asserted.
The purpose of the fingerprint is to
associate the timestamp with the
packet. Thus, it can be the sequence
ID field from the PTP packet or some
other unique field of the packet, to
validate both the fingerprint and
timestamp collected from the CPU.
tx_egress_timestamp_96b_valid
Out 1 When asserted, this signal qualifies
the timestamp on tx_egress_
timestamp_96b_data[] for the
transmit frame whose fingerprint is
specified by tx_egress_timestamp_
96b_fingerprint[] .
5-18
1588v2 Interfaces
UG-01144
2014.12.15
Altera Corporation
Interface Signals for LL Ethernet 10G MAC
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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