Altera Parallel Flash Loader IP Manuel d'utilisateur

Parallel Flash Loader IP Core User Guide2015.01.23UG-01082SubscribeSend FeedbackThis document describes how to instantiate the Parallel Flash Loader (

The PFL IP core provides JTAG interface logic to convert the JTAG stream provided by the Quartus IIsoftware and to program the CFI flash memory device

The PFL IP core instantiated in the Altera CPLD functions as a bridge between the CPLD JTAG program‐ming interface and the quad SPI flash memory devic

Programming NAND FlashYou can use the JTAG interface in Altera CPLDs to program the NAND flash memory device with thePFL IP core. The NAND flash memor

You can use the PFL IP core to either program the flash memory devices, configure your FPGA, or both;however, to perform both functions, create separa

Figure 9: Micron J3 Flash Memory in 8-Bit ModeThe address connection between the PFL IP core and the flash memory device are the same.232221---210PFLa

Figure 12: Spansion and Micron M28, M29 Flash Memory in 16-Bit ModeThe address bit numbers in the PFL IP core and the flash memory device are the same

Table 4: Option Bits Sector FormatOffset address 0x80 stores the .pof version required for programming flash memory. This .pof version applies to alle

Figure 13: Implementing Page Mode and Option Bits in the CFI Flash Memory Device• The end address depends on the density of the flash memory device. F

CFI Device (Megabit) Address Range16 0x0000000–0x01FFFFF32 0x0000000–0x03FFFFF64 0x0000000–0x07FFFFF128 0x0000000–0x0FFFFFF256 0x0000000–0x1FFFFFF512

For the FPP configuration scheme, the enhanced bitstream compression feature helps achieve higherconfiguration data compression ratio and faster confi

Note: The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it is<home directory>/altera/ &

Using Remote System UpgradeWhen you instantiate the PFL IP core in the Altera CPLD for FPP or PS configuration, you can use thefeatures in the PFL IP

Figure 18: Transitions Between Different Configurations in Remote System Upgrade• The remote system upgrade feature in the PFL IP core does not restri

image address. Altera recommends that you write-protect the factory image blocks in the flashmemory device.Implementing Remote System Upgrade with the

period. You must periodically reset this timer by asserting the pfl_reset_watchdog pin before thewatchdog time-out period. If the timer does not reset

Related InformationAN478: Using FPGA-Based Parallel Flash Loader with the Quartus II SoftwareProvides more information about using the FPGA-based PFL

To convert the .sof files to a .pof, follow these steps:1. On the File menu, click Convert Programming Files.2. For Programming file type, specify Pro

• Typical bitstream compression feature1. Select .sof under SOF Data.2. Click Properties, and then turn on the Compression option.3. Click OK.• Enhanc

The clock signal on the TCK pins is internally constrained to the maximum frequency supported by theselected JTAG programming hardware. It is not nece

To constrain the synchronous input and output signals in the TimeQuest analyzer, follow these steps:1.Run full compilation for the PFL design. Ensure

Type Port Constraint Type Delay ValueOutput asynchro‐nousfpga_nconfig set_false_path —pfl_flash_access_request set_false_path —flash_nce set_false_pat

Manufacturer Product Family Data Width Density (Megabit) Device Name(1)(2)P30 1664 28F640P30128 28F128P30256 28F256P30512 28F512P301000 28F00AP302000

Related Information• ModelSim-Altera Software SupportProvides more information about simulation setup in ModelSim-Altera software.• Altera Knowledge C

Related Information• Simulating PFL Design on page 29• About Using the ModelSim Software with the Quartus II SoftwareProvides more information about o

After reading the option bits for page 0, the PFL IP core waits for a period of time before the configurationstarts. The flash_data remains at 0×ZZ wi

5. Select the .pof generated for the flash memory device. The .pof for the flash memory device is attachedto the .pof of the CPLD.6. Add other program

To add a new CFI flash memory device to the database or update a CFI flash device in the database, followthese steps:1. In the Programmer window, on t

Related InformationSupported Flash Memory Devices on page 2Programming Multiple Flash Memory DevicesThe PFL IP core supports multiple-flash programmin

Figure 23: Single-Device Configuration Using the PFL With the Controllerpfl_nresetpfl_flash_access_grantedflash_addrflash_dataflash_nweflash_nceflash_

intend to program, do not overwrite the Nios II processor image when you program the flash memorydevice with other user data.If you do not want to sto

Figure 25: Nios II Processor and PFL Accessing the Flash Memory Device SequenceNios II processor connectsto the flash deviceThe PFL megafunction pulls

Third-party Programmer SupportYou can program the flash memory using a third-party programmer instead of using Parallel Flash LoaderIP core. To progra

Manufacturer Product Family Data Width Density (Megabit) Device Name(1)(2)G18 16512 MT28GU512AAA1EGC-0SIT1024 MT28GU01GAAA1EGC-0SITM58BW3216M58BW16FTM

Options Value DescriptionNumber of flashdevices used• CFI Parallel Flash: 1–16• Altera Active Serial ×4: 1,2,4• Quad SPI Flash: 1,2,4• NAND Flash: 1,2

Options Value DescriptionByte address forreserved block area—Specifies the start address of the reserved blockarea for bad block management.NAND flash

Options Value DescriptionFlash access time —Specifies the access time of the flash. You can getthe maximum access time that a flash memorydevice requi

Options Value DescriptionTime period beforethe watchdog timertimes out— Specifies the time out period of the watchdogtimer. The default time out perio

SignalsThis section contains information about the PFL IP core input and output signals.Table 14: PFL SignalsFor maximum FPGA configuration DCLK frequ

Pin Description Weak Pull-UpFunctionfpga_nstatus Input 10-kW Pull-Up ResistorConnects to the nSTATUS pin of the FPGA.This pin must be released high be

Pin Description Weak Pull-UpFunctionflash_nce[] Output — Connects to the nCE pin of the flash memorydevice. A low signal enables the flashmemory devic

Pin Description Weak Pull-UpFunctionfpga_dclk Output — Connects to the DCLK pin of the FPGA.Clock input data to the FPGA device duringconfiguration. T

Pin Description Weak Pull-UpFunctionflash_io3[] Output — The fourth bit of the data bus to or from thequad SPI flash. If you use more than onequad SPI

Table 15: FPP and PS Mode Equations for the PFLFlash Access ModeConfigura‐tion DataOptionFlash DataWidth (bits)DCLK Ratio = 1, 2, 4, or 8 (9)FPP Mode

Manufacturer Product Family Data Width Density (Megabit) Device Name(1)(2)Eon SiliconSolutionEN29LV 16 16 EN29LV160BEN29GL 1632 EN29LV320B128 EN29GL12

Flash Access ModeConfigura‐tion DataOptionFlash DataWidth (bits)DCLK Ratio = 1, 2, 4, or 8 (9)FPP Mode PS ModeBurst ModeNormal4Cflash = 4Ccfg = DCLK R

Flash Access ModeConfigura‐tion DataOptionFlash DataWidth (bits)DCLK Ratio = 1, 2, 4, or 8 (9)FPP Mode PS Mode• For Normal Mode and Burst Mode:Caccess

Example 2: Normal Mode• Normal mode configuration time calculation:.rbf size for EP2S15 = 577KB = 590,848 BytesConfiguration mode = FPP without data c

Example 3: Page Mode• Page mode configuration time calculation:.rbf size for EP2S15 = 577 KB = 590,848 BytesConfiguration mode = FPP without data comp

Example 4: Burst Mode• Burst mode configuration time calculation:.rbf size for EP2S15 = 577KB = 590,848 BytesConfiguration mode = FPP without data com

Example 5: Single Quad SPI Flash• Single quad SPI flash configuration time calcualtion.rbf size for EP2S15 = 577KB = 590,848 BytesConfiguration mode =

Document Revision HistoryDate Version ChangesJanuary 2015 2015.01.23• Corrected DATA width in PFL IP core With Dual P30 or P33 CFIFlash Memory Devices

Date Version ChangesJuly 2010 1.0 Converted from AN386: Using the Parallel Flash Loader With theQuartus II Software.UG-010822015.01.23Document Revisio

Manufacturer Product Family Density (Megabit) Device NameMacronixMX25L8MX25L8035EMX25L8036E16MX25L1635DMX25L1635EMX25L1636DMX25L1636E32MX25L3225DMX25L

Related InformationSpansion WebsiteSupported Schemes and FeaturesThe PFL IP core allows you to configure the FPGA in passive serial (PS) or fast passi

Figure 2: Quartus II IP CatalogSearch and filter IP for your target deviceDouble-click to customize, right-click for informationNote: The IP Catalog i

Figure 3: IP Parameter EditorsView IP portand parameter detailsApply preset parameters forspecific applicationsSpecify your IP variation nameand targe