Altera Low Latency Ethernet 10G MAC Manuel d'utilisateur Page 32
- Page / 109
- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Figure 3-8: Normal Frame with Preamble Passthrough Mode, Padding Bytes Insertion, and Source
Address Insertion Enabled
The following diagram shows the transmission of good frames with preamble passthrough mode, padding
bytes insertion, and source address insertion enabled.
0 3
7c91_5b8d
*5 *_fff *fb *4 *5 *3 *f *0 *9 *a *1 *3 *0 *3 *0
0707_0707
*b *1 *_fff *ff *2 *0 *b *0 *e *5 *5 *6 *3 *0 *4 *c *0 *8 *d
f 1
7c
d1 ff 2b 00 5b 60 8e 65 25 36 13 10 04
81
bf ff 0098 2f 5d de 4b 4e 54 53 13 60 a1
83 001d 45 e3 5b 09 bb db 10 e8 86 a9
d5 0024 f5 f3 2f 20 69 ba 21 53 f0 83
ff 44
ff fb
5b
8d
fb 0422 00 5b 60 8e 65 25 36 13 10d1 ff
07
fd7c 00 38
*5 a133 2f 5d de 4b 4e 54 53 13 60*5 ff
07
00 7a
*5 a944 45 e3 5b 09 bb db 10 e8 86*5
07
00 9cff 00
*5 8355 f5 f3 2f 20 69 ba 21 53 f0*5
07
00 eeff 00
tx_312_5_clk
avalon_st_tx_startofpacket
avalon_st_tx_valid
avalon_st_tx_ready
avalon_st_tx_endofpacket
avalon_st_tx_error
avalon_st_tx_empty[1:0]
avalon_st_tx_data[31:0]
xgmii_tx_data[31:0]
xgmii_tx_control[3:0]
avalon_st_tx_data[31:24]
avalon_st_tx_data[23:16]
avalon_st_tx_data[15:8]
avalon_st_tx_data[7:0]
xgmii_tx_data[7:0]
xgmii_tx_data[15:8]
xgmii_tx_data[23:16]
xgmii_tx_data[31:24]
0
92e6_9b29 0faa_4s5e
92 0f
e6 aa
9b 4a
29 5e
0707_0707
f0
07
07
07
07
Figure 3-9: Back-to-back Transmission of Normal Frames with Source Address Insertion Enabled.
The following diagram shows back-to-back transmission of normal frames with source address insertion
enabled. The MAC primary address registers are set to 0x000022334455.
0 3
0
8190_a0b0 *a7 *8d *ed *05 *56 *f0 *d6 *44 *95 *f4 *38 *03 *31 *0b *7a *00 *0_a0b0 *d2 *96 *01 *5c *43 *cb *e3 b4c1_cafd *f0 *4c 0023_456
0707_0707 *fb *55 *81 *c0 *22 *3d *f5 *08 *d6 *7e *51 *37 *1a *95 *a2 *9f *96 *b9 *e3 *be *7_0707 *fb *55 *81 *c0 *22
f 1 0 e f 1 0
81 c0 15 3d f5 08 d6 7e 51 37 1a 95 a2 31 96 b9 e3 81 c0 d6 88 00 7b 31 0e b4 49 25 00
90 d0 83 61 1c 75 e3 f4 7b 99 cd bc 83 85 5a 00 90 d0 07 08 0a 40 9f 76 c1 04 8b 23
a0 e7 35 1b 2f ff 5a b1 fc 06 b2 a8 ca 54 0d 4f 00 a0 cd 39 00 1d 05 11 57 ca e1 27 45
b0 a7 8d ed 05 56 f0 d6 44 95 f4 38 ca 31 0b 7a 00 b0 d2 96 01 5c 43 cb e3 fd f0 4c 67
07 fb 55 81 c0 22 3d f5 08 d6 7e 51 37 1a 95 a2 9f 96 b9 e3 be 07 fb 55 81 c0 22
07 55 90 d0 33 61 1c 75 e3 f4 7b 99 cd bc 83 85 5a c7 fd 07 55 90 d0 33
07 55 a0 00 44 1b 2f ff 5a b1 fc 06 b2 a8 ca 54 0d 4f 53 07 55 a0 00 44
07 55 d5 b0 00 55 ed 05 56 f0 d6 44 95 f4 38 03 31 0b 7a 88 07 55 d5 b0 00 55
tx_312_5_clk
avalon_st_tx_startofpacket
avalon_st_tx_valid
avalon_st_tx_ready
avalon_st_tx_endofpacket
avalon_st_tx_error
avalon_st_tx_empty[1:0]
avalon_st_tx_data[31:0]
xgmii_tx_data[31:0]
xgmii_tx_control[3:0]
avalon_st_tx_data[31:24]
avalon_st_tx_data[23:16]
avalon_st_tx_data[15:8]
avalon_st_tx_data[7:0]
xgmii_tx_data[7:0]
xgmii_tx_data[15:8]
xgmii_tx_data[23:16]
xgmii_tx_data[31:24]
3-10
TX Timing Diagrams
UG-01144
2014.12.15
Altera Corporation
Functional Description of LL Ethernet 10G MAC
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
Produits connexes et manuels pour Instruments de mesure Altera Low Latency Ethernet 10G MAC
Instruments de mesure Altera Nios II Embedded Evaluation Kit Cyclone III Editio Manuel d'utilisateur
(3 pages)
(3 pages)
Instruments de mesure Altera Nios II Embedded Evaluation Kit Cyclone III Editio Manuel d'utilisateur
(80 pages)
(80 pages)
Instruments de mesure Altera Phase-Locked Loop Reconfiguration IP Core Manuel d'utilisateur
(51 pages)
(51 pages)
Instruments de mesure Altera Serial Digital Interface (SDI) MegaCore Function Manuel d'utilisateur
(140 pages)
(140 pages)
Instruments de mesure Altera 100G Development Kit, Stratix V GX Edition Manuel d'utilisateur
(44 pages)
(44 pages)
Instruments de mesure Altera Stratix V Avalon-MM Interface for PCIe Solutions Manuel d'utilisateur
(184 pages)
(184 pages)
Instruments de mesure Altera 10-Gbps Ethernet MAC MegaCore Function Manuel d'utilisateur
(175 pages)
(175 pages)
Instruments de mesure Altera Triple Speed Ethernet MegaCore Function Manuel d'utilisateur
(223 pages)
(223 pages)
© 2020, manymanuals.fr. Tous droits réservés | 0.049 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Commentaires sur ces manuels