Altera Low Latency Ethernet 10G MAC Manuel d'utilisateur Page 97
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Noté. / 5. Basé sur avis des utilisateurs
XGMII RX Signals
Table 5-12: XGMII Receive Signals
Signal Condition Direction Width Description
xgmii_rx_
data[]
Use legacy Ethernet
10G MAC XGMII
interface disabled.
Enable 10GBASE-R
register mode
disabled.
In 32 4-lane RX data bus. Lane 0 starts from
the least significant bit.
• Lane 0: xgmii_rx_data[7:0]
• Lane 1: xgmii_rx_data[15:8]
• Lane 2: xgmii_rx_data[23:16]
• Lane 3: xgmii_rx_data[31:24]
Use legacy Ethernet
10G MAC XGMII
interface disabled.
Enable 10GBASE-R
register mode
enabled.
In 64
8-lane SDR XGMII receive data. This
signal connects directly to the Native
PHY IP core.
• Lane 0: xgmii_rx_data[7:0]
• Lane 1: xgmii_rx_data[15:8]
• Lane 2: xgmii_rx_data[23:16]
• Lane 3: xgmii_rx_data[31:24]
• Lane 4: xgmii_rx_data[39:32]
• Lane 5: xgmii_rx_data[47:40]
• Lane 6: xgmii_rx_data[55:48]
• Lane 7: xgmii_rx_data[63:56]
xgmii_rx_
control[]
Use legacy Ethernet
10G MAC XGMII
interface disabled.
Enable 10GBASE-R
register mode
disabled.
In 4 Control bits for each lane in xgmii_rx_
data[].
• Lane 0: xgmii_rx_control[0]
• Lane 1: xgmii_rx_control[1]
• Lane 2: xgmii_rx_control[2]
• Lane 3: xgmii_rx_control[3]
Use legacy Ethernet
10G MAC XGMII
interface disabled.
Enable 10GBASE-R
register mode
enabled.
In 8
8-lane SDR XGMII receive control. This
signal connects directly to the
NativePHY IP core.
• Lane 0: xgmii_rx_control[0]
• Lane 1: xgmii_rx_control[1]
• Lane 2: xgmii_rx_control[2]
• Lane 3: xgmii_rx_control[3]
• Lane 4: xgmii_rx_control[4]
• Lane 5: xgmii_rx_control[5]
• Lane 6: xgmii_rx_control[6]
• Lane 7: xgmii_rx_control[7]
UG-01144
2014.12.15
XGMII RX Signals
5-15
Interface Signals for LL Ethernet 10G MAC
Altera Corporation
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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