Altera Low Latency Ethernet 10G MAC Manuel d'utilisateur Page 90
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Signal Direction Width Description
avalon_st_tx_pfc_gen_
data[]
In n
(4–16)
n = 2 x Number of PFC queues parameter.
Each pair of bits is associated with a priority queue. Bits
0 and 1 are for priority queue 0, bits 2 and 3 are for
priority queue 1, and so forth. Set the respective pair of
bits to the following values to trigger the specified
actions for the corresponding priority queue.
• 0x0: Stops pause frame generation for the
corresponding queue.
• 0x1: Generates an XON pause frame for the
corresponding queue.
• 0x2: Generates an XOFF pause frame for the
corresponding queue. The MAC IP core sets the
pause quanta field in the pause frame to the value in
the tx_pauseframe_quanta register.
• 0x3: Reserved.
avalon_st_rx_pfc_
pause_data[]
Out n
(2–8)
n = Number of PFC queues parameter.
When the MAC RX receives a pause frame, it asserts bit
n of this signal when the pause quanta for the n
th
queue
is valid (Pause Quanta Enable [n] = 1) and greater than
0. For each quanta unit, the MAC RX asserts bit n for
eight clock cycle.
The MAC RX deasserts bit n of this signal when the
pause quanta for the n
th
queue is valid (Pause Quanta
Enable [n] = 1) and equal to 0. The MAC RX also
deasserts bit n when the timer expires.
avalon_st_rx_pause_
length_valid
Out 1 This signal is present in the MAC RX only variation.
The MAC IP core asserts this signal to request its link
partner to suspend data transmission. When asserted, a
valid pause quanta is available on the avalon_st_rx_
pause_length_data bus.
avalon_st_rx_pause_
length_data[]
Out 16 This signal is present only in the MAC RX only
variation.
Specifies the pause quanta in unit of quanta, where 1
unit = 512 bits time.
Avalon-ST Status Interface
Avalon-ST TX Status Signals
5-8
Avalon-ST Status Interface
UG-01144
2014.12.15
Altera Corporation
Interface Signals for LL Ethernet 10G MAC
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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