Altera Low Latency Ethernet 10G MAC Manuel d'utilisateur Page 39
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Figure 3-16: Back-to-back Transmission of Normal Frames with Preamble Passthrough Mode Enabled
The following diagram shows back-to-back reception of normal frames with preamble passthrough mode
and padding bytes and CRC removal enabled.
rx_312_5_clk
avalon_st_rx_startofpacket
avalon_st_trx_endofpacket
avalon_st_rx_valid
avalon_st_rx_ready
avalon_st_rx_error[5:0]
avalon_st_rx_empty[1:0]
avalon_st_rx_data[31:0]
xgmii_rx_data[31:0]
xgmii_rx_control[3:0]
avalon_st_rx_data[31:24]
avalon_st_rx_data[23:16]
avalon_st_rx_data[15:8]
avalon_st_rx_data[7:0]
xgmii_rx_data[7:0]
xgmii_rx_data[15:8]
xgmii_rx_data[23:16]
xgmii_rx_data[31:24]
*52
*1
*38 *10 *1 *a *5 *0 *a *f3 *1c *af *9 *_34a8 *7 *88 *5 *f_ff*52 *c *b4 *9 *c *94 *b *e *c *3 *e1 *df *e8 *7 *6a *ff *_8601 *07 0707_0
*9
*
*20 *7 *fb *a *f_ff*fff *1 *81 *1 *4 *fb *a *e *4f *85 *c8 *e *fe *92 *0 *1 fd 0707_0707*6 *c
c
0
f 1 0 f 1 0 1 0 1 0 1 0 1 0 1 0 1
89
16
20 07 fb 3a ff a1 81 64 fb 6a 8e 4f 85 c8 4e fe 92 70 91 fd 0766 0c
34
5b
fd 07 88 3a ff f5 dd 2f 34 c2 8e ce 0e 3a 20 1e a4 26 a6 86 07c9 2a
85
34
94 07 88 3a ff 85 00 1e 59 29 6d b3 3a 1f 38 f0 05 b3 29 0790 87
a8
a9
07 88 d5 ff 26 bc b4 e9 9c 94 bc e3 e1 df e8 37 6a ff 079b ee 01 68
ff
3c
fa c2 85 53 26 36 34 f2 35 f4 16 89 07 fb 3a ff a1 81 64 fb 66 0c 6a 8e 4f 85 c8 4e fe 92 70 fd 07
c5
ff
92 f5 6d 41 3c b0 1d 20 4e 32 5b 34 07 88 3a ff f5 dd 2f 34 c2 8e c9 2a ce 0e 3a 20 1e a4 26 a6 86 07
6c
81
36 0e 34 8a 30 92 c4 50 f5 80 34 85 07 88 3a ff 85 00 1e 59 90 87 29 6d b3 3a 1f 38 f0 05 b3 07
52
11
38 10 51 0a 95 b0 0a f3 1c af a9 a8 07 88 d5 ff 26 bc b4 e9 c2 94 9b ee bc e3 e1 df e8 37 6a ff 01 07
0 02
00
Flow Control
The MAC IP core implements the following flow control mechanisms:
• IEEE 802.3 flow control—implements the IEEE 802.3 Annex 31B standard to manage congestion.
When the MAC IP core experiences congestion, the core sends a pause frame to request its link
partner to suspend transmission for a given period of time. This flow control is a mechanism to
manage congestion at the local or remote partner. When the receiving device experiences congestion,
it sends an XOFF pause frame to the emitting device to instruct the emitting device to stop sending
data for a duration specified by the congested receiver. Data transmission resumes when the emitting
device receives an XON pause frame (pause quanta = zero) or when the timer expires.
• Priority-based flow control (PFC)—implements the IEEE 802.1Qbb standard. PFC manages
congestion based on priority levels. It supports up to 8 priority queues. When the receiving device
experiences congestion on a priority queue, it sends a PFC frame requesting the emitting device to stop
transmission on the priority queue for a duration specified by the congested receiver. When the
receiving device is ready to receive transmission on the priority queue again, it sends a PFC frame
instructing the emitting device to resume transmission on the priority queue.
Note:
Altera recommends that you enable only one type of flow control at any one time.
IEEE 802.3 Flow Control
This section describes the pause frame reception and transmission in the IEEE 802.3 flow control.
UG-01144
2014.12.15
Flow Control
3-17
Functional Description of LL Ethernet 10G MAC
Altera Corporation
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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