Altera Low Latency Ethernet 10G MAC Manuel d'utilisateur Page 72
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Word
Offset
Register Name Description Access HW Reset
Value
0x10A tx_fns_adjustment_mult_
speed
Static timing adjustment in fractional
nanoseconds on the TX datapath for 10M/
100M/1G operations.
• Bits 15:0—adjustment period in
fractional nanoseconds.
• Bits 31:16—reserved. Set these bits to 0.
Configure this register before you enable
the MAC IP core for operations.
RW 0x0
0x10C tx_ns_adjustment_mult_
speed
Static timing adjustment in nanoseconds
on the TX datapath for 10M/100M/1G
operations.
• Bits 15:0—adjustment period in
nanoseconds.
• Bits 31:16—reserved. Set these bits to 0.
Configure this register before you enable
the MAC IP core for operations.
RW 0x0
Calculating TX Timing Adjustments
You can derive the required timing adjustments in ns and fns from the hardware PMA delay.
Table 4-11: Hardware PMA Delay
Type Device PMA Mode
(bit)
Latency
(9)
MAC Configurations
Digital
Arria V GZ and
Stratix V
40 123 UI 10GbE or 10G of 10M-10GbE
32 99 UI 10GbE
10 53 UI 1G/100M/10M of 10M-10GbE
Analog
(10)
Arria V GZ and
Stratix V
— –1.1 ns All
The example below shows the required calculation for a 10M – 10GbE design targeting a Stratix V device.
Table 4-12: Example: Calculating Timing Adjustments for 10M – 10GbE Design in Stratix V Device
Step Description 10G 10M, 100M or 1G
1 Identify the digital
latency for the device.
For Stratix V using the PMA mode of
40 bits, the digital latency is 123 UI.
For Stratix V using the PMA mode
of 10 bits, the digital latency is 53
UI.
(9)
For 10G: 1 UI = 97 ps; for 10M/100M/1G: 1 UI = 800 ps
(10)
Valid for the HSSI clock routing using periphery clock. Other clocking scheme might result in deviation of a
few ns.
4-20
Calculating TX Timing Adjustments
UG-01144
2014.12.15
Altera Corporation
Configuration Registers for LL Ethernet 10G MAC
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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