Altera Low Latency Ethernet 10G MAC Manuel d'utilisateur Page 69
- Page / 109
- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Word
Offset
Register Name Description Access HW Reset
Value
0x00B0 rx_frame_spaddr0_0 You can specify up to four 6-byte
supplementary addresses:
• rx_framedecoder_spaddr0_0/1
• rx_framedecoder_spaddr1_0/1
• rx_framedecoder_spaddr2_0/1
• rx_framedecoder_spaddr3_0/1
Configure the supplementary addresses
before you enable the MAC RX datapath.
Map the supplementary addresses to the
respective registers in the same manner as
the primary MAC address. Refer to the
description of primary_mac_addr0 and
primary_mac__addr1.The MAC IP core
uses the supplementary addresses to filter
unicast frames when the following
conditions are set:
• The use of the supplementary addresses
are enabled using the respective bits in
the rx_frame_control register.
• The en_allucast bit of the rx_frame_
control register is set to 0.
RW 0x0
0x00B1
rx_frame_spaddr0_1
0x00B2 rx_frame_spaddr1_0
0x00B3 rx_frame_spaddr1_1
0x00B4 rx_frame_spaddr2_0
0x00B5 rx_frame_spaddr2_1
0x00B6 rx_frame_spaddr3_0
0x00B7 rx_frame_spaddr3_1
0x00C0 rx_pfc_control
(8)
• Bits 7:0—enables priority-based flow
control on the RX datapath. Setting bit n
enables priority-based flow control for
priority queue n. For example, setting
rx_pfc_control[0] enables queue 0.
• Bits 15:9—reserved.
• Bit 16—configures the forwarding of
priority-based control frames to the
client.
0: Drops the control frames.
1: Forwards the control frames to the
client.
• Bits 31:17—reserved.
Configure this register before you enable
the MAC IP core for operations.
RW
0x1
(8)
This register is used only when you turn on the Enable priority-based flow control (PFC) option. It is
reserved when not used.
UG-01144
2014.12.15
RX Configuration and Status Registers
4-17
Configuration Registers for LL Ethernet 10G MAC
Altera Corporation
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
Produits connexes et manuels pour Instruments de mesure Altera Low Latency Ethernet 10G MAC
Instruments de mesure Altera Nios II Embedded Evaluation Kit Cyclone III Editio Manuel d'utilisateur
(3 pages)
(3 pages)
Instruments de mesure Altera Nios II Embedded Evaluation Kit Cyclone III Editio Manuel d'utilisateur
(80 pages)
(80 pages)
Instruments de mesure Altera Phase-Locked Loop Reconfiguration IP Core Manuel d'utilisateur
(51 pages)
(51 pages)
Instruments de mesure Altera Serial Digital Interface (SDI) MegaCore Function Manuel d'utilisateur
(140 pages)
(140 pages)
Instruments de mesure Altera 100G Development Kit, Stratix V GX Edition Manuel d'utilisateur
(44 pages)
(44 pages)
Instruments de mesure Altera Stratix V Avalon-MM Interface for PCIe Solutions Manuel d'utilisateur
(184 pages)
(184 pages)
Instruments de mesure Altera 10-Gbps Ethernet MAC MegaCore Function Manuel d'utilisateur
(175 pages)
(175 pages)
Instruments de mesure Altera Triple Speed Ethernet MegaCore Function Manuel d'utilisateur
(223 pages)
(223 pages)
© 2020, manymanuals.fr. Tous droits réservés | 0.016 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Commentaires sur ces manuels