Altera Low Latency Ethernet 10G MAC Manuel d'utilisateur Page 48
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Figure 3-22: Overview of IEEE 1588v2 Feature
IEEE 1588v2
Tx Logic
IEEE 1588v2
Rx Logic
PTP Software
Stack
Time-of-Day
Clock
PHY
Tx
PHY
Rx
10GbE MAC IP
10GBASE-R PHY IP
tx_path_delay
rx_path_delay
Timestamp &
User Fingerprint
Correction
Time of Day
Timestamp Aligned to
Receive Frame
tx_egress_timestamp_request
tx_ingress_timestamp
tx_time_of_day
rx_time_of_day
Transmit Datapath
The IEEE 1588v2 feature supports 1-step and 2-step clock synchronizations on the transmit datapath.
• For 1-step clock synchronization,
• Timestamp insertion depends on the PTP device and message type.
• The MAC function inserts a timestamp in the PTP packet when the client specifies the Timestamp
field offset and asserts Timestamp Insert Request.
• Depending on the PTP device and message type, the MAC function updates the residence time in
the correction field of the PTP packet when the client asserts
tx_etstamp_ins_ctrl_residence_time_update and Correction Field Update. The residence
time is the difference between the egress and ingress timestamps.
• For PTP packets encapsulated using the UDP/IPv6 protocol, the MAC function performs UDP
checksum correction using extended bytes in the PTP packet.
• The MAC function recomputes and reinserts CRC-32 into the PTP packets after each timestamp or
correction field insertion.
• The format of timestamp supported includes 1588v1 and 1588v2
• For 2-step clock synchronization, the MAC function returns the timestamp and the associated
fingerprint for all transmit frames when the client asserts tx_egress_timestamp_request_valid.
The following table summarizes the timestamp and correction field insertions for various PTP messages
in different PTP clocks.
3-26
Transmit Datapath
UG-01144
2014.12.15
Altera Corporation
Functional Description of LL Ethernet 10G MAC
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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