Altera Low Latency Ethernet 10G MAC Manuel d'utilisateur Page 2
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Contents
About LL Ethernet 10G MAC............................................................................. 1-1
Features......................................................................................................................................................... 1-2
Release Information.....................................................................................................................................1-3
Device Family Support................................................................................................................................1-3
Definition: Device Support Level...................................................................................................1-4
Performance and Resource Utilization.....................................................................................................1-4
Resource Utilization........................................................................................................................ 1-4
TX and RX Latency..........................................................................................................................1-5
Getting Started with LL Ethernet 10G MAC...................................................... 2-1
Introduction to Altera IP Cores.................................................................................................................2-1
Installing and Licensing IP Cores..............................................................................................................2-2
Specifying IP Core Parameters and Options............................................................................................2-2
Parameterizing the IP Core........................................................................................................................ 2-3
Parameter Settings....................................................................................................................................... 2-4
Generated Files.............................................................................................................................................2-6
Simulating Altera IP Cores in other EDA Tools..................................................................................... 2-7
Upgrading Outdated IP Cores................................................................................................................... 2-8
Migrating IP Cores to a Different Device.................................................................................................2-9
Design Considerations..............................................................................................................................2-11
Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC.................................2-11
Timing Constraints........................................................................................................................2-12
Functional Description of LL Ethernet 10G MAC............................................. 3-1
Architecture..................................................................................................................................................3-1
Interfaces.......................................................................................................................................................3-2
Frame Types..................................................................................................................................................3-4
TX Datapath................................................................................................................................................. 3-4
Padding Bytes Insertion..................................................................................................................3-4
Address Insertion.............................................................................................................................3-4
CRC-32 Insertion.............................................................................................................................3-5
XGMII Encapsulation..................................................................................................................... 3-6
Inter-Packet Gap Generation and Insertion................................................................................ 3-7
XGMII Transmission...................................................................................................................... 3-7
Unidirectional Feature.................................................................................................................... 3-8
TX Timing Diagrams.......................................................................................................................3-9
RX Datapath............................................................................................................................................... 3-13
XGMII Decapsulation...................................................................................................................3-13
CRC Checking................................................................................................................................3-13
Address Checking..........................................................................................................................3-14
Frame Type Checking................................................................................................................... 3-14
TOC-2
Low Latency Ethernet 10G MAC User Guide
Altera Corporation
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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