Altera Low Latency Ethernet 10G MAC Manuel d'utilisateur Page 36
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Address Checking
The MAC RX can accept frames with the following address types:
• Unicast address—bit 0 of the destination address is 0.
• Multicast address—bit 0 of the destination address is 1.
• Broadcast address—all 48 bits of the destination address are 1.
The MAC RX always accepts broadcast frames. By default, it also receives all unicast and multicast frames
unless configured otherwise in the EN_ALLUCAST and EN_ALLMCAST bits of the rx_frame_control register.
When the EN_ALLUCAST bit is set to 0, the MAC RX filters unicast frames received. The MAC RX accepts
only unicast frames with a destination address that matches the primary MAC address specified in the
primary_mac_addr0 and primary_mac_addr1 registers. If any of the supplementary address bits are set to
1 (EN_SUPP0/1/2/3 in the rx_frame_control register), the MAC RX also checks the destination address
against the supplementary addresses in the rx_frame_spaddr*_* registers.
When the EN_ALLMCAST bit is set to 0, the MAC RX drops all multicast frames. This condition does not
apply to global multicast pause frames.
Frame Type Checking
The MAC RX checks the length/type field to determine the frame type:
• Length/type < 0x600—The field represents the payload length of a basic Ethernet frame. The MAC RX
continues to check the frame and payload lengths.
• Length/type >= 0x600—The field represents the frame type.
• Length/type = 0x8100—VLAN or stacked VLAN tagged frames. The MAC RX continues to check
the frame and payload lengths.
• Length/type = 0x8808—Control frames. The next two bytes are the Opcode field which indicates
the type of control frame. For pause frames (Opcode = 0x0001) and PFC frames (Opcode =
0x0101), the MAC RX proceeds with pause frame processing. By default, the MAC RX drops all
control frames. If configured otherwise (FWD_CONTROL bit in the rx_frame_control register = 1),
the MAC RX forwards control frames to the client.
• For other field values, the MAC RX forwards the receive frame to the client.
Length Checking
The MAC RX checks the frame and payload lengths of basic, VLAN tagged, and stacked VLAN tagged
frames. The MAC RX does not drop frames with invalid length but sets the error bits accordingly.
3-14
Address Checking
UG-01144
2014.12.15
Altera Corporation
Functional Description of LL Ethernet 10G MAC
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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