Altera Low Latency Ethernet 10G MAC Manuel d'utilisateur Page 37
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Frame Length
The frame length must be at least 64 (0x40) bytes and not exceed the following maximum value for the
different frame types:
• Basic—The value in the rx_frame_maxlength register.
• VLAN tagged—The value in the rx_frame_maxlength register plus four bytes when the
rx_vlan_detection[0] register bit is 0; or the value in the rx_frame_maxlength register when the
rx_vlan_detection[0] register bit is set to 1.
• Stacked VLAN tagged—The value in the rx_frame_maxlength register plus eight bytes when the
rx_vlan_detection[0] register bit is 0; or the value in the rx_frame_maxlength register when the
rx_vlan_detection[0] register bit is set to 1.
The following error bits represent frame length violations:
• avalon_st_rx_error[2]—undersized frames.
• avalon_st_rx_error[3]—oversized frames.
Payload Length
The MAC IP core checks the payload length for frames other than control frames when the VLAN and
stacked VLAN detection is disabled. The MAC RX keeps track of the actual payload length as it receives a
frame and checks the actual payload length against the length/type or client length/type field. The payload
length must be between 46 (0x2E) and 1500 (0x5DC). For VLAN and stacked VLAN frames, the
minimum payload length is 42 (0x2A) or 38 (0x26) respectively and not exceeding the maximum value of
1500 (0x5DC).
For an invalid payload length, the MAC RX sets the avalon_st_rx_error[4] bit to 1. This error occurs
when the actual payload length is less than the value of the length/type field. If the actual payload length is
more than the value of the length/type field, the MAC RX assumes that the frame contains excessive
padding and does not set this error bit to 1.
CRC and Padding Bytes Removal
By default, the MAC RX forwards receive frames to the client without removing the CRC field and
padding bytes from the frames. You can configure the MAC RX to remove the CRC field by setting the
rx_padcrc_control register to 1. To remove both the CRC field and padding bytes, set the
rx_padcrc_control register to 3.
When enabled, the MAC RX removes padding bytes from receive frames whose payload length is less
than the following values for the different frame types:
• 46 bytes for basic frames
• 42 bytes for VLAN tagged frames
• 38 bytes for stacked VLAN tagged frames
The MAC RX removes padding bytes only when the VLAN and stacked VLAN detection is enabled
(rx_vlan_detection[0] = 0). Otherwise, the MAC RX does not remove padding bytes even if padding
bytes removal is enabled.
UG-01144
2014.12.15
Frame Length
3-15
Functional Description of LL Ethernet 10G MAC
Altera Corporation
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- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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