Altera Low Latency Ethernet 10G MAC Manuel d'utilisateur Page 86
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Table 5-3: Error Correction Signals
Signal Direction Width Description
ecc_err_det_corr Out 1 The MAC IP core can indicate detected and
corrected ECC errors using the ecc_status
register, or both the register and this signal.
This signal indicates the state of the ecc_
status[0] register bit when the ecc_
enable[0] register bit is set to 1. This signal
is 0 when the ecc_enable[0] register bit is
set to 1.
ecc_err_det_uncorr Out 1 The MAC IP core can indicate detected and
uncorrected ECC errors using the ecc_
status register, or both the register and
this signal.
This signal indicates the state of the ecc_
status[1] register bit when the ecc_
enable[1] register bit is set to 1. This signal
is 0 when the ecc_enable[1] register bit is
set to 1.
Unidirectional Signals
The unidirectional signals are present only when you turn on the Unidirectional feature option.
Table 5-4: Unidirectional Signals
Signal Direction Width Description
unidirectional_en Out 1
When asserted, this signal indicates the
state of the tx_unidir_control register bit
0.
unidirectional_remote_
fault_dis
Out 1
When asserted, this signal indicates the
state of the tx_unidir_control register bit
1.
Avalon-MM Programming Signals
The Avalon-MM programming signals apply to all operating modes.
Table 5-5: Avalon-MM Programming Signals
Signal Direction Width Description
csr_address[] In 10 Use this bus to specify the register address to read
from or write to.
5-4
Unidirectional Signals
UG-01144
2014.12.15
Altera Corporation
Interface Signals for LL Ethernet 10G MAC
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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