Altera Low Latency Ethernet 10G MAC Manuel d'utilisateur Page 57
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Access Definition
RW1C Read and write 1 to clear. Writing 0 has no effect. Writing 1 clears the bit if the bit has
been set to 1 by the IP core. The client takes precedence over the IP core.
Primary MAC Address
Table 4-4: Primary MAC Address
Word
Offset
Register Name Description Access HW Reset
Value
0x0010 primary_mac_addr0 6-byte primary MAC address. Configure
this register with a non-zero value before
you enable the MAC IP core for operations.
Map the primary MAC address as follows:
• primary_mac_addr0: Lower four bytes
of the address.
• primary_mac_addr1[15:0]: Upper two
bytes of the address.
• primary_mac_addr1[31:16]: Reserved.
Example
If the primary MAC address is 00-1C-23-
17-4A-CB, set primary_mac_addr0 to
0x23174ACB and primary_mac_addr1 to
0x0000001C.
Usage
On transmit, the MAC IP core uses this
address to fill the source address field in
control frames. For data frames from the
client, the MAC IP core replaces the source
address field with the primary MAC address
when the tx_src_addr_override register
is set to 1.
On receive, the MAC IP core uses this
address to filter unicast frames when the
EN_ALLUCAST bit of the rx_frame_control
register is set to 0. The MAC IP core drops
frames whose destination address is
different from the value of the primary
MAC address.
RW 0x0
0x0011
primary_mac_addr1
MAC Reset Control Register
This register is used only in 10G, 1G/10G, and 10M/100M/1G/10G operating modes.
UG-01144
2014.12.15
Primary MAC Address
4-5
Configuration Registers for LL Ethernet 10G MAC
Altera Corporation
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- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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