Altera Low Latency Ethernet 10G MAC Manuel d'utilisateur Page 87
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Noté. / 5. Basé sur avis des utilisateurs
Signal Direction Width Description
csr_read In 1 Assert this signal to request a read.
csr_readdata[] Out 32 Data read from the specified register. The data is
valid when thecsr_waitrequest signal is
deasserted.
csr_write In 1 Assert this signal to request a write.
csr_writedata[] In 32 Data to be written to the specified register. The data
is written when thecsr_waitrequest signal is
deasserted.
csr_waitrequest Out 1
When asserted, this signal indicates that the MAC
IP core is busy and not ready to accept any read or
write requests.
• When you have requested for a read or write,
keep the control signals to the Avalon-MM
interface constant while this signal is asserted.
The request is complete when it is deasserted.
• This signal can be high or low during idle cycles
and reset. Therefore, the user application must
not make any assumption of its assertion state
during these periods.
Avalon-ST Data Interfaces
Avalon-ST TX Data Interface Signals
Table 5-6: Avalon-ST TX Data Interface Signals
Signal Direction Width Description
avalon_st_tx_
startofpacket
In 1 Assert this signal to indicate the beginning of the
TX data on the Avalon-ST interface.
avalon_st_tx_
endofpacket
In 1 Assert this signal to indicate the end of the TX data
on the Avalon-ST interface.
avalon_st_tx_valid In 1 Assert this signal to indicate that avalon_st_tx_
data[] and other signals on this interface are valid.
avalon_st_tx_ready Out 1 When asserted, indicates that the MAC IP core is
ready to accept data. The reset value for this signal
is 1'b1. However, the user logic should not rely on
this default reset behavior to operate.
avalon_st_tx_error In 1 Assert this signal to indicate that the current TX
packet contains errors.
avalon_st_tx_data[] In 32 TX data from the client.
UG-01144
2014.12.15
Avalon-ST Data Interfaces
5-5
Interface Signals for LL Ethernet 10G MAC
Altera Corporation
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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