Altera Low Latency Ethernet 10G MAC Manuel d'utilisateur Page 13
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Related Information
• Parameter Settings on page 2-4
Parameter Settings
You customize the MAC IP core by specifying the parameters on the parameter editor in the Quartus II
software. The parameter editor enables only the parameters that are applicable to the selected speed.
Parameter Value Description
Speed 10G, 1G/10G, 10M/
100M/1G/10G
Select the desired speed. By default, 10 Gbps is
selected.
If you turn on the Enable 10GBASE-R register
mode parameter, only 10 Gbps is available.
Datapath options TX only, RX only, TX &
RX
Select the MAC variation to instantiate.
• TX only—instantiates MAC TX.
• RX only—instantiates MAC RX.
• TX & RX—instantiates both MAC TX and
RX.
If you turn on the Enable 10GBASE-R register
mode parameter, only the TX & RX option is
available.
Enable ECC on memory
blocks
On, Off Turn on this option to enable error detection
and correction on memory blocks.
Enable preamble pass-
through mode
On, Off Turn on this option to enable preamble pass-
through mode. You must also set the tx_
preamble_control, rx_preamble_control,
and rx_custom_preamble_forward registers to
1. When enabled, the MAC IP core allows
custom preamble in data frames on the
transmit and receive datapaths.
This parameter applies only to 10Gbps MAC
variations.
This parameter is not available if you turn on
the Enable 10GBASE-R register mode
parameter.
Enable priority-based flow
control (PFC)
On, Off Turn on this option to enable PFC. You must
also set the tx_pfc_priority_enable[n]bit to
1 and specify the number of priority queues in
the Number of PFC queues field.
This parameter applies only to 10Gbps MAC
variations.
This parameter is not available if you turn on
the Enable 10GBASE-R register mode
parameter.
2-4
Parameter Settings
UG-01144
2014.12.15
Altera Corporation
Getting Started with LL Ethernet 10G MAC
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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