Altera Low Latency Ethernet 10G MAC Manuel d'utilisateur Page 31
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Table 3-2: Register Field and Link Status
Bit 0 Register Field Bit 1 Register Field Link Status TX XGMII Interface Behavior
Don't care Don't care No link fault Continue to allow normal packet transmission.
0 Don't care Local fault Immediately override the current content with
remote fault sequence.
1 0 Local fault Continue to send packet if there is one.
Otherwise, override the IPG/IDLE bytes with
remote fault sequence.
(1)
1 1 Local fault Continue to allow normal packet transmission
(similar to no link fault).
0 Don't care Remote fault Immediately override the current content with
IDLE control characters.
1 Don't care Remote fault Continue to allow normal packet transmission
(similar to no link fault).
TX Timing Diagrams
Figure 3-7: Normal Frame
The following diagram shows the transmission of a normal frame.
tx_312_5_clk
avalon_st_tx_startofpacket
avalon_st_tx_valid
avalon_st_tx_ready
avalon_st_tx_endofpacket
avalon_st_tx_error
avalon_st_tx_empty[1:0]
avalon_st_tx_data[31:0]
xgmii_tx_data[31:0]
xgmii_tx_control[3:0]
avalon_st_tx_data[31:24]
avalon_st_tx_data[23:16]
avalon_st_tx_data[15:8]
avalon_st_tx_data[7:0]
xgmii_tx_data[7:0]
xgmii_tx_data[15:8]
xgmii_tx_data[23:16]
xgmii_tx_data[31:24]
0 3 0
0f8e_8236 0023_4567 *5 *1 *2 *2 *5 *b *c *7 *e
*d *5 *3 *e *5 *0
cc6b_d355
0707_0707 *b *5 *0 *9 *1 *0 *c *e *b
*6 *1 *0 *b *7 *6
*d *d *d *2 0707_0707
f 1 0 e f
0f 00 89 f1 00 fc ce 6b 26 01 e0
0b 87 a6 7d 4d 5d
cc
8e
23
ab c7 2f 8c 3f 9f d9 77 59
71 e5 3a 42 00
6b
82 45 c4 e9 fb 00 62 f7 80 84 09
c5 21 65 4b b1 00
d3
36 67 d5 61 d2 82 85 4b fc 67 9e
9d 45 23 ee a5 00
55
07 7dfb 55 00 89 f1 00 fc ce 6b
26 01 e0 0b 87 a6
07
07
3a
55 23 ab c7 2f 8c 3f 9f
d9 77 71 e5
07
07 4b55 45 c4 e9 fb 00 62 f7
80 84 09 c5 21 65
07
07 ee55 d5 67 d5 61 d2 82 85 4b
fc 67 9e 8d 45 23
07
a2
4d 5d
fd
42 13
b1 8a
a5 d0
59
(1)
At least a full column of IDLE (four IDLE characters) must precede the remote fault sequence.
UG-01144
2014.12.15
TX Timing Diagrams
3-9
Functional Description of LL Ethernet 10G MAC
Altera Corporation
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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