Altera Low Latency Ethernet 10G MAC Manuel d'utilisateur Page 43
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- Table des matières
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Noté. / 5. Basé sur avis des utilisateurs
Figure 3-18: CSR Reset
csr, tx, rx clocks
csr_rst_n
tx_rst_n
rx_rst_n
When you assert csr_rst_n , you must
also assert tx_rst_n and rx_rst_n .
Hold the reset signals active for at least 3 clock
periods of the slowest clock.
Deassert csr_rst_n no later than
tx_rst_n and rx_rst_n .
You can configure the registers after csr_rst_n
is deasserted, but before data transfer begins.
Table 3-3: TX and RX Datapaths Reset
No Stage Steps
1 Ensure no data transfer in progress.
1. Set the tx_packet_control[0] bit to 1 to disable the
TX datapath; the rx_transfer_control[0] bit to
disable the RX datapath.
2. Check the tx_transfer_status[8] bit for a value of
0 to ensure that no TX data transfer is in progress; the
rx_transfer_status[8] bit for RX path. Alterna‐
tively, wait for a period of time.
2 Trigger reset.
1. Assert the tx_rst_n signal or the rx_rst_n signal to
reset the MAC TX or MAC RX respectively. You can
also trigger the reset by setting the mac_reset_
control[0] bit or the mac_reset_control[8] bit to
1 to reset the MAC TX or MAC RX respectively.
2. Hold the reset signal active for at least three clock
cycles.
3 Stop reset.
1. Release the reset signal only when the clocks are
stable.
2. Wait for 500 ns to ensure the reset is fully complete.
3. Clear the statistics counters.
4 Resume data transfer.
1. Clear the tx_packet_control[0] bit to enable the
TX datapath; the rx_transfer_control[0] bit to
enable the RX datapath.
Supported PHYs
You can connect the LL 10GbE MAC IP core to a PHY IP core using XGMII, GMII, or MII interfaces.
UG-01144
2014.12.15
Supported PHYs
3-21
Functional Description of LL Ethernet 10G MAC
Altera Corporation
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- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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