Altera Low Latency Ethernet 10G MAC Manuel d'utilisateur Page 7
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Release Information
The following table lists information about this release of the LL Ethernet 10G MAC IP core.
Table 1-1: Release Information
Item Description
Version 15.0
Release Date May 2015
Ordering Code IP-10GEUMAC
Product ID ID 0119
Vendor ID 6AF7
Altera verifies that the current version of the Quartus II software compiles the previous version of each
MegaCore function, if this MegaCore function was included in the previous release. Any exceptions to
this verification are reported in the MegaCore IP Library Release Notes and Errata. Altera does not verify
compilation with MegaCore function versions older than the previous release.
Related Information
• MegaCore IP Library Release Notes and Errata
• Errata for Low Latency Ethernet 10G MAC MegaCore function in the Knowledge Base
Device Family Support
The IP core provides the following support for Altera device families.
Table 1-2: Device Family Support for LL Ethernet 10G MAC
Device Family Support
Minimum Speed Grade
With 1588 Feature Without 1588 Feature
Arria
®
10 Preliminary -I2 -I3
Arria V GZ Final -I3, -C3 -I4, -C4
Stratix
®
V Final -I3, -C3 -I4, -C4
The following table lists possible configurations and the devices each configuration supports:
Table 1-3: Device Family Support for Configurations
Configuration Arria V GX/GT/
GZ
Arria 10 Stratix V
10G MAC with 10GBASE-R PHY Arria V GZ No Yes
10G MAC with 10GBASE-R PHY and IEEE
1588v2
Arria V GZ No Yes
UG-01144
2014.12.15
Release Information
1-3
About LL Ethernet 10G MAC
Altera Corporation
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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