Altera Low Latency Ethernet 10G MAC Manuel d'utilisateur Page 20
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6. To regenerate the new IP variation for the new target device, click Generate. When generation is
complete, click Close.
7. Click Finish to complete migration of the IP core. Click OK if you are prompted to overwrite IP core
files. The Device Family column displays the new target device name when migration is complete. The
migration process replaces <my_ip>.qip with the <my_ip>.qsys top-level IP file in your project.
Note: If migration does not replace <my_ip>.qip with <my_ip>.qsys, click Project > Add/Remove
Files in Project to replace the file in your project.
8. Review the latest parameters in the parameter editor or generated HDL for correctness. IP migration
may change ports, parameters, or functionality of the IP core. During migration, the IP core's HDL
generates into a library that is different from the original output location of the IP core. Update any
assignments that reference outdated locations. If your upgraded IP core is represented by a symbol in a
supporting Block Design File schematic, replace the symbol with the newly generated <my_ip>.bsf
after migration.
Note: The migration process may change the IP variation interface, parameters, and functionality.
This may require you to change your design or to re-parameterize your variant after the
Upgrade IP Components dialog box indicates that migration is complete. The Description
field identifies IP cores that require design or parameter changes.
Related Information
Altera IP Release Notes
Design Considerations
Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC
Altera recommends the following migration path. Migrating your existing design in this manner allows
you to take advantage of the benefits of LL Ethernet 10G MAC—low resource count and low latency.
Migration—32-bit Datapath on Avalon-ST Interface
This migration path implements 32-bit datapath on the Avalon ST and Avalon-MM interfaces.
1. Instantiate the LL Ethernet 10G MAC IP core in your design. If you are using a PHY with 64-bit SDR
XGMII interface, turn on the Use legacy Ethernet 10G MAC XGMII Interface option.
2. Modify your user logic to accommodate 32-bit datapaths on Avalon-ST TX and RX data interfaces.
3. Ensure that tx_312_5_clk and rx_312_5_clk are connected to 312.5-MHz clock sources. Altera
recommends that you use the same clock source for these clock signals.
4. Update the register offsets to the offsets of the LL Ethernet 10G MAC. The configuration registers of
the LL Ethernet 10G MAC allow access to new features such as error correction and detection on
memory blocks.
5. If you turn on the Use legacy Ethernet 10G MAC XGMII Interface option, add a 156.25 MHz clock
source for tx_156_25_clk and rx_156_25_clk. This 156.25 MHz clock source must be rise-to-rise
synchronous to the 312.5 MHz clock source.
6. Ensure that csr_clk is within 125 MHz to 156.25 MHz. Otherwise, some statistic counters may not be
accurate.
UG-01144
2014.12.15
Design Considerations
2-11
Getting Started with LL Ethernet 10G MAC
Altera Corporation
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- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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