Altera Low Latency Ethernet 10G MAC Manuel d'utilisateur Page 109
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Noté. / 5. Basé sur avis des utilisateurs
Date Version Changes
June 2014 2014.06.30
• Improved the performance and resource utilization.
• Added a new feature—Unidirectional Ethernet.
• Added a new parameter—Enable Unidirectional feature.
• Added Unidirectional registers and signals.
• Added information about PMA analog and digital delay for IEEE
1588v2 MAC registers.
• Edited the bit description of avalon_st_rxstatus_error[] signal.
• Added more information about the avalon_st_pause_data[0] bit
signal to indicate that the transmission of XON pause frames only
trigger for one time after XOFF pause frames regardless of how long
the avalon_st_pause_data[0] is asserted.
• Updated the statistics registers description.
• Edited the bit description of tx_underflow_counter0, tx_
underflow_counter1, rx_pktovrflow_etherStatsDropE-
vents,rx_pktovrflow_error signals.
• Edited the bit description of csr_clk signal to state that the
recommended clock frequency for this signal is 125 Mhz–156.25 Mhz
regardless of whether you select register-based or memory-based
statistics counter.
• Updated the tx_rst_n and rx_rst_n signals description to reflect the
change from asynchronous reset to synchronous reset.
• Updated the csr_waitrequest signal description.
December 2013
2013.12.02 Initial release
UG-01144
2014.12.15
Low Latency Ethernet 10G MAC User Guide Document Revision History
A-3
Additional Information
Altera Corporation
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- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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