Altera Low Latency Ethernet 10G MAC Manuel d'utilisateur Page 26
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Frame Types
The MAC IP core supports the following frame types:
• Basic Ethernet frames, including jumbo frames.
• VLAN and stacked VLAN frames.
• Control frames, which include pause and PFC frames.
TX Datapath
The MAC TX receives the client payload data with the destination and source addresses, and appends
various control fields depending on the MAC configuration.
Figure 3-3: Typical Client Frame at TX Interface
Client - MAC Tx Interface
(optional)
Client Frame
MAC Frame
Destination
Addr[47:0]
Source
Addr[47:0]
Type/
Length[15:0]
Payload
[<p-1>:0]
Destination
Addr[47:0]
SFD[7:0]
Preamble
[55:0]
CRC32
[31:0]
PAD [<s>]
Source
Addr[47:0]
Client-Defined Preamble
[63:0]
(optional)
Type/
Length[15:0]
Payload
[<p-1>:0]
PAD [<s>]
CRC32
[31:0]
EFD[7:0]
IPG
[<l-1>:0]
Frame Length
(1) (2)
(3)
Padding Bytes Insertion
By default, the MAC TX inserts padding bytes (0x00) into TX frames to meet the following minimum
payload length:
• 46 bytes for basic frames
• 42 bytes for VLAN tagged frames
• 38 bytes for stacked VLAN tagged frames
Ensure that CRC-32 insertion is enabled when padding bytes insertion is enabled.
You can disable padding bytes insertion by setting the tx_pad_control register to 0. When disabled, the
MAC IP core forwards the frames to the PHY-side interface without padding. Ensure that the minimum
payload length is met; otherwise the current frame may get corrupted. You can check for undersized
frames by referring to the statistics collected.
Address Insertion
By default, the MAC TX retains the source address received from the client. You can configure the MAC
TX to replace the source address with the primary MAC address specified in the tx_addrins_macaddr0
and tx_addrins_macaddr1 registers by setting the bit tx_src_addr_override[0] to 1.
3-4
Frame Types
UG-01144
2014.12.15
Altera Corporation
Functional Description of LL Ethernet 10G MAC
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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