Altera Low Latency Ethernet 10G MAC Manuel d'utilisateur Page 41
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
The following figure shows the transmission of an XON pause frame. The MAC sets the destination
address field to the global multicast address, 01-80-C2-00-00-01 (0x010000c28001) and the source address
to the MAC primary address configured in the tx_addrins_macaddr0 and tx_addrins_madaddr1
registers.
Figure 3-17: XON Pause Frame Transmission
tx_clk_clk
FB 55 01 00 FD
xgmii_tx_control[3]
xgmii_tx_data[31:24]
xgmii_tx_control[2]
xgmii_tx_data[23:16]
xgmii_tx_control[1]
xgmii_tx_data[15:8]
xgmii_tx_control[0]
xgmii_tx_data[7:0]
00 88 88 96
55 55 80 00
01 CC 08 96
55 55 C2 00
EE AA 96
55 D5 00 00
CC EE 01 96
Priority-Based Flow Control
This section describes the PFC frame reception and transmission. Follow these steps to use the PFC:
1. Turn on the Priority-based flow control (PFC) parameter and specify the number of priority levels
using the Number of PFC priorities parameter. You can specify between 2 to 8 PFC priority levels.
2. Set the following registers.
• On the transmit datapath:
• Set tx_pauseframe_enable to 0 to disable the IEEE 802.3 flow control.
• Set tx_pfc_priority_enable[n] to 1 to enable the PFC for priority queue n.
• On the receive datapath:
• Set the IGNORE_PAUSE bit in the rx_decoder_control register to 1 to disable the IEEE 802.3
flow control.
• Set the PFC_IGNORE_PAUSE_n bit in the rx_pfc_control register to 0 to enable the PFC.
3. Connect the avalon_st_tx_pfc_gen_data signal to the corresponding RX client logic and the
avalon_st_rx_pfc_pause_data signal to the corresponding TX client logic.
4. You have the option to configure the MAC RX to forward the PFC frame to the client by setting the
FWD_PFC bit in the rx_pfc_control register to 1. By default, the MAC RX drops the PFC frame after
processing it.
UG-01144
2014.12.15
Priority-Based Flow Control
3-19
Functional Description of LL Ethernet 10G MAC
Altera Corporation
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- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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