Altera Low Latency Ethernet 10G MAC Manuel d'utilisateur Page 84
- Page / 109
- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Signal Operating
Mode
Direction Width Description
tx_156_25_clk 10G, 1G/10G,
10M/100M/
1G/10G
In 1
156.25-MHz clock for the MAC TX
datapath when you choose to
maintain compatibility with the 64-
bit Ethernet 10G MAC on the
Avalon-ST TX data interface or
XGMII. This feature is not available
when the Enable 10GBASE-R
register mode is enabled.
Altera recommends that this clock
and tx_312_5_clk share the same
clock source. This clock must be
synchronous to tx_312_5_clk.
Their rising edges must align and
must have 0 ppm and phase-shift.
tx_rst_n All In 1 Active-low reset for the MAC TX
datapath.
rx_312_5_clk 10G, 1G/10G,
10M/100M/
1G/10G
In 1 312.5-MHz clock for the MAC RX
datapath when the Enable
10GBASE-R register mode is
disabled. You may use the same
clock source for this clock and tx_
312_5_clk.
rx_xcvr_clk 10G In 1 322.265625-MHz clock for the MAC
RX datapath when the Enable
10GBASE-R register mode is
enabled.
rx_156_25_clk 10G, 1G/10G,
10M/100M/
1G/10G
In 1
156.25-MHz clock for the MAC RX
datapath when you choose to
maintain compatibility with the 64-
bit Ethernet 10G MAC on the
Avalon-ST RX data interface or
XGMII. This feature is not available
when the Enable 10GBASE-R
register mode is enabled.
Altera recommends that you use the
same clock source for this clock and
rx_312_5_clk. This clock must be
synchronous to rx_312_5_clk.
Their rising edges must align and
must have 0 ppm and phase-shift.
5-2
Clock and Reset Signals
UG-01144
2014.12.15
Altera Corporation
Interface Signals for LL Ethernet 10G MAC
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
Produits connexes et manuels pour Instruments de mesure Altera Low Latency Ethernet 10G MAC
Instruments de mesure Altera Nios II Embedded Evaluation Kit Cyclone III Editio Manuel d'utilisateur
(3 pages)
(3 pages)
Instruments de mesure Altera Nios II Embedded Evaluation Kit Cyclone III Editio Manuel d'utilisateur
(80 pages)
(80 pages)
Instruments de mesure Altera Phase-Locked Loop Reconfiguration IP Core Manuel d'utilisateur
(51 pages)
(51 pages)
Instruments de mesure Altera Serial Digital Interface (SDI) MegaCore Function Manuel d'utilisateur
(140 pages)
(140 pages)
Instruments de mesure Altera 100G Development Kit, Stratix V GX Edition Manuel d'utilisateur
(44 pages)
(44 pages)
Instruments de mesure Altera Stratix V Avalon-MM Interface for PCIe Solutions Manuel d'utilisateur
(184 pages)
(184 pages)
Instruments de mesure Altera 10-Gbps Ethernet MAC MegaCore Function Manuel d'utilisateur
(175 pages)
(175 pages)
Instruments de mesure Altera Triple Speed Ethernet MegaCore Function Manuel d'utilisateur
(223 pages)
(223 pages)
© 2020, manymanuals.fr. Tous droits réservés | 0.037 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Commentaires sur ces manuels