Altera Avalon Verification IP Suite Manuel d'utilisateur télécharger pdf (Page 83)

set_enable_a_readid_sequence()

set_enable_a_readid_sequence()Prototype:

Verilog HDL: Boolean

VHDL: N.A.

Arguments:

voidReturns:

Enables an assertion that verifies if the readid sequence follows the sequence

of the transactionid.

Description:

Verilog HDLLanguage support:

set_enable_a_read_response_sequence()

set_enable_a_read_response_sequence()Prototype:

Verilog HDL: Boolean

VHDL: N.A.

Arguments:

voidReturns:

Enables an assertion that ensures readdatavalid is asserted while read is

asserted for the same read transfer.

Description:

Verilog HDLLanguage support:

set_enable_a_read_response_timeout()

set_enable_a_read_response_timeout()Prototype:

Verilog HDL: Boolean

VHDL: N.A.

Arguments:

voidReturns:

Enables an assertion that ensures readdatavalid is asserted within

maximum allowed timeout period. Disabled when either readdatavalid is

not supported or the maximum allowed timeout period is less than 1.

Description:

Verilog HDLLanguage support:

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set_enable_a_readid_sequence()

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Altera Avalon Verification IP Suite Manuel d'utilisateur Page 83