Altera Avalon Verification IP Suite Manuel d'utilisateur télécharger pdf (Page 17)

Clock_stop()

clock_stop()Prototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Turns off the clock.Description:

Verilog HDLLanguage support:

get_run_state()

get_run_state()Prototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

bitReturns:

Returns the state of the clock source; 1=running, 0=stop.Description:

Verilog HDLLanguage support:

get_version()

string get_version()Prototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

stringReturns:

Returns BFM version as a string of three integers separated by periods. For example,

version 10.1 sp1 is encoded as "10.1.1".

Description:

Verilog HDLLanguage support:

Clock Source BFM

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Clock_stop()

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Altera Avalon Verification IP Suite Manuel d'utilisateur Page 17