Altera Avalon Verification IP Suite Manuel d'utilisateur télécharger pdf (Page 155)

signal_fatal_error

signal_fatal_errorPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Notifies the testbench that a fatal error has occurred in this module.Description:

Verilog HDLLanguage support:

signal_transaction_fifo_overflow

signal_transaction_fifo_overflowPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Notifies the testbench that the FIFO is full and further transactions are

dropped.

Description:

Verilog HDLLanguage support:

signal_transaction_fifo_threshold

signal_transaction_fifo_thresholdPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Notifies the testbench that the transaction FIFO threshold level has exceeded.Description:

Verilog HDLLanguage support:

signal_transaction_received

signal_transaction_receivedPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Notifies the testbench that a transaction has been received and queued.Description:

Verilog HDLLanguage support:

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Altera Avalon Verification IP Suite Manuel d'utilisateur Page 155