Altera Avalon Verification IP Suite Manuel d'utilisateur télécharger pdf (Page 167)

set_valid_transaction_<role name>_out()

void set_valid_transaction_<role name>_out()Prototype:

Verilog HDL: index, new_value

VHDL: index, new_value

Arguments:

voidReturns:

Sets the value of the valid transaction to the <role name>_out output port.Description:

Verilog HDL, VHDLLanguage support:

signal_all_transactions_complete

signal_all_transactions_completePrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Triggers when all the queued output and input transactions are completely

retrieved.

Description:

Verilog HDLLanguage support:

signal_fatal_error

signal_fatal_errorPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Notifies the testbench that a fatal error has occurred in this module.Description:

Verilog HDLLanguage support:

Tri-State Conduit BFM

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