Altera Avalon Verification IP Suite Manuel d'utilisateur télécharger pdf (Page 181)

get_result_delay()

int get_result_delay()Prototype:

Verilog HDL: None

VHDL: result_delay, bfm_id, req_if(bfm_id)

Arguments:

Width of the data (ci_data_t)that can contain the following variables:

• [Word_width-1:0]

• [Ext_width-1:0]

• [Addr_width-1:0]

Returns:

Returns the result delay.Description:

Verilog HDL, VHDLLanguage support:

get_result_queue_size()

int get_result_queue_size(int size)Prototype:

Verilog HDL: None

VHDL: result_queue_size, bfm_id, req_if(bfm_id)

Arguments:

int size.Returns:

Returns the number of results in the queue.Description:

Verilog HDL, VHDLLanguage support:

get_result_value()

string get_result_value()Prototype:

Verilog HDL: None

VHDL: result_value, bfm_id, req_if(bfm_id)

Arguments:

Width of the data (ci_data_t)that can contain the following variables:

• [Word_width-1:0]

• Ext_width-1:0]

• [Addr_width-1:0]

Returns:

Returns the instruction result.Description:

Verilog HDL, VHDLLanguage support:

Nios II Custom Instruction Master BFM

Altera Corporation

Send Feedback

get_result_delay()

14-6

1 2 ... 176 177 178 179 180 181 182 183 184 185 186 ... 223 224

Pas de commentaire

Altera Avalon Verification IP Suite Manuel d'utilisateur Page 181