Altera Avalon Verification IP Suite Manuel d'utilisateur télécharger pdf (Page 124)

set_transaction_sop()

set_transaction_sop(bit sop)Prototype:

Verilog HDL: sop

VHDL: sop, bfm_id, req_if(bfm_id)

Arguments:

voidReturns:

Sets the status of the start of packet signal in the out-going transaction.Description:

Verilog HDL, VHDLLanguage support:

signal_fatal_error

signal_fatal_errorPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that a fatal error has occurred. It terminates the simulation.Description:

Verilog HDLLanguage support:

signal_max_transaction_queue_size

signal_max_transaction_queue_sizePrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that the pending transaction queue size threshold has been exceeded.Description:

Verilog HDLLanguage support:

signal_min_transaction_queue_size

signal_min_transaction_queue_sizePrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that the pending transaction queue size is below the minimum threshold.Description:

Verilog HDLLanguage support:

Avalon-ST Source BFM

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Altera Avalon Verification IP Suite Manuel d'utilisateur Page 124