Altera Avalon Verification IP Suite Manuel d'utilisateur télécharger pdf (Page 46)

set_response_timeout()

void set_response_timeout(int cycles)Prototype:

Verilog HDL: int cycles

VHDL: int cycles, bfm_id, req_if(bfm_id)

Arguments:

voidReturns:

Sets the number of cycles that may elapse before response time out. Disable time-

out by setting the value to 0.

Description:

Verilog HDL, VHDLLanguage support:

signal_all_transactions_complete

signal_all_transactions_completePrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that all queued transactions have completed.Description:

Verilog HDLLanguage support:

signal_command_issued

signal_command_issuedPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that the currently pending command has been driven to the interface.Description:

Verilog HDLLanguage support:

Avalon-MM Master BFM

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