Altera Avalon Verification IP Suite Manuel d'utilisateur télécharger pdf (Page 136)

signal_sink_ready_deassert

signal_sink_ready_deassertPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that sink_ready is deasserted, turning on back pressure.Description:

Verilog HDLLanguage support:

signal_transaction_received

signal_transaction_receivedPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that the transaction has been received and queued.Description:

Verilog HDLLanguage support:

Avalon-ST Sink BFM

Altera Corporation

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signal_sink_ready_deassert

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