Altera JESD204B IP Manuel d'utilisateur

JESD204B IP Core User GuideLast updated for Altera Complete Design Suite: 15.0SubscribeSend FeedbackUG-011422015.05.04101 Innovation DriveSan Jose, CA

F ParameterThis parameter indicates how many octets per frame per lane that the JESD204B link is operating in. Youmust set the F parameter according t

Figure below illustrates the converter sample to transceiver lane mapping operation in the transport layer.Each converter sample has N bits, M convert

Figure 5-7: User Data Format that Feeds into the Transport Layer and Output to the Link LayerConverter Device, MxN bits, S Samples per Single Converte

F = 1F1_FRAMCLK_DIV=1(32)1st frameclkjesd204_tx_datain[31:0] ={F8F12, F0F4}Case1: M=1, S=2 M0S0=F0F4,M0S1=F8F12Case2: M=2, S=1 M0S0=F0F4,M1S0=F8F122nd

F = 2F2_FRAMCLK_DIV=11st frameclkjesd204_tx_datain[63:0] ={F12F13,F8F9,F4F5, F0F1}Case1: M=1, S=4 M0S0=F0F1, M0S1=F4F5,M0S2=F8F9, M0S3=F12F13atCase2:

F = 4Data Out {F12, F13, F14,F15}{F8, F9, F10, F11} {F4, F5, F6, F7} {F0, F1, F2, F3}Table 5-9: Data Mapping for F=8, L=4F = 8Supported Mand SM*S=16 f

Figure 5-8: TX Error ReportingThe jesd204_tx_data_valid signal deasserts for one frame_clk and cannot be sampled by the link_clk.txframe_clktxlink_clk

Figure 5-9: RX Path Assembler Block DiagramDeassemblingMultiplexingRX Controljesd204_rx_link_datain[(L*32)-1:0]jesd204_rx_link_data_validjesd204_rx_li

Parameter Description ValueF2_FRAMECLK_DIV Only applies to cases where F=2.The divider ratio on the frame_clk. The deassembler always uses thepost-div

Signal Clock Domain Direction DescriptionBetween Avalon- ST and Transport Layerjesd204_rx_dataout[(OUTPUT_BUS_WIDTH)-1:0]rxframe_clkOutputRX data to t

Signal Clock Domain Direction Descriptionjesd204_rx_link_data_validrxlink_clk InputIndicates whether the jesd204_rx_link_datain[] is valid or invalid.

Device Family Core Variation Bonding Mode Configuration Maximum Number ofLanes (L)Arria V GZArria 10Stratix VPHY onlyBonded 32 (2)Non-bonded 32 (2)MAC

Signal Clock Domain Direction Descriptioncsr_l[4:0] (35)mgmt_clkInputIndicates the number of active lanes for the link.This 5-bit bus represents the L

Signal Clock Domain Direction Descriptioncsr_f[7:0] (35)mgmt_clkInputIndicates the number of octets per frame. This 8-bit bus represents the F value i

Figure 5-10: RX Operation BehaviorThis figure shows the data transmission for a system configuration of LMF = 112, N = 12, N' = 16, S =1.Operatio

clock cycle depending on the F and FRAMECLK_DIV parameters selected based on the frame clock tolink clock relationship.Figure 5-11: RX Data ReceptionJ

F = 1F1_FRAMCLK_DIV=11st frameclkcnt=0 :jesd204_rx_dataout[31:0] ={F8F12, F0F4}Case1: M=1, S=2 M0S0=F0F4, M0S1=F8F12Case2: M=2, S=1 M0S0=F0F4, M1S0=F8

F = 2F2_FRAMCLK_DIV=11st frameclkcnt=0:jesd204_rx_dataout[63:0] ={F12F13,F8F9,F4F5, F0F1}Case1: M=1, S=4 M0S0=F0F1, M0S1=F4F5,M0S2=F8F9, M0S3=F12F13Ca

Table 5-16: Data Mapping for F=8, L=4F = 8Lane L3 L2 L1 L0Data In linkclkT0{F24, F25, F26,F27}{F16, F17, F18,F19}{F8, F9, F10, F11} {F0, F1, F2, F3}Da

RX LatencyThe RX latency is defined as the time needed to fully transfer a 32-bit data in a lane(jesd204_rx_link_datain*) to the Avalon-ST interface (

example. The subsequent 13 bits represent the starting address of the data sent. The last 8 bits are registerdata.For a 32-bit SPI transaction, each S

Figure 5-15: Control Unit Process FlowPower-Up and ResetAssert Transceiver(user-triggered), Frame, and CSR ResetSPI ConfigurationAssert Link, Frame, a

Device FamilyPMA SpeedGradeFPGA FabricSpeed GradeData RateLink Clock FMAX (MHz)Enable HardPCS (Gbps)Enable Soft PCS(Gbps) (3)Stratix V 3 1, 2, 3, or 4

Figure 5-16: Example of MIF Format and Content-- MIF content for ADCWIDTH=24; -- the size of data in bits DEPTH=8; -- the size of

System ParametersTable 5-18: System Parameter SettingsThis table lists the parameters exposed at the system level.Parameter Value (37)Default Descript

Parameter Value (37)Default DescriptionFEEDBACK_TAP 6, 5, 14, 18,286 Defines the feedback tap for the PRBS pattern generator andchecker. This is an in

Mode Link L M F ReferenceClockFrameClockLinkClockF1_FRAMECLK_DIVF2_FRAMECLK_DIVBonded/Non-bonded 1 8 1 1 307.2 153.6 153.6 4Bonded/Non-bonded 1 8 2 1

Figure 5-18: Datapath of Multiple JESD204B Links32321616Avalon-STAvalon-STAvalon-STAvalon-STTransport Layer 0JESD204B IP Duplex Core 0 (LMF = 112)Patt

System Interface SignalsTable 5-21: Interface SignalsSignal ClockDomainDirection DescriptionClocks and Resetsdevice_clk— Input Device clock signal fro

Signal ClockDomainDirection Descriptionrx_sysref[LINK-1:0] link_clkInput RX SYSREF signal for JESD204B Subclass 1implementation.tx_dev_sync_n[LINK-1:0

Signal ClockDomainDirection Descriptionrx_seriallpbken[LINK*L-1:0]— Input Assert this signal to enable internal serial loopback inthe duplex transceiv

Signal ClockDomainDirection Descriptionavst_usr_din[(FRAMECLK_DIV*LINK*M*S*N)-1:0]frame_clkInputTX data from the Avalon-ST source interface. Thesource

Signal ClockDomainDirection Descriptionavst_usr_dout[(FRAMECLK_DIV*LINK*M*S*N)-1:0]frame_clkOutputRX data to the Avalon-ST sink interface. Thetranspor

Table 2-5: JESD204B IP Core Resource UtilizationThe numbers of ALMs and logic registers in this table are rounded up to the nearest 10.Note: The resou

Signal ClockDomainDirection Descriptiontest_mode[3:0] frame_clkInput Specifies the operation mode.• 0000—Normal mode. The design example takesdata fro

Figure 5-19: Dynamic Reconfiguration Block Diagram (For 28 nm Device Families—Stratix V and ArriaV)JESD204B IP Core (Duplex)CSR PHYPHY MIFROMSPI Maste

Figure 5-20: Dynamic Reconfiguration Block Diagram (For 20 nm Device Families—Arria 10)JESD204B IP Core (Duplex)CSR PHYSPI MasterClock MIFROMDAC MIFRO

DATA_RADIX=BIN;CONTENT BEGIN 0 : 00000000000000000000000000111110; -- START OF MIF 1 : 00000000000000000000000000000100; 2 : 0000

[88..91] : 0000000000000000; 92 : 0000000000011111; -- End of MIF opcodeDownscale TX PLL Configuration MIF 93 : 0000000000100001; -- St

27 : 3FFFFFF; -- End of MIFEND;xcvr_cdr_combined.mifMaximum Configuration MIFCONTENT BEGIN 00 : 006DF02; -- Start of MIF 01 :

.. 11 : 1111111111111111; -- End of MIF [12..15] : 0000000000000000; END;ADC/DAC/CLKThe content for ADC/DAC/CLK MIF is vendor-specific. The gen

Note: For more information about the JESD204B design example testbench, refer to the README_DESIGN_EXAMPLE.txt file located in the <example_design_

To run the Tcl script using the Quartus II sofware, follow these steps:1. Launch the Quartus II software.2. On the View menu, click Utility Windows an

JESD204B IP Core Deterministic LatencyImplementation Guidelines62015.05.04UG-01142SubscribeSend FeedbackSubclass 1 and Subclass 2 modes support determ

Device Family Data Path Number ofLanesALMs ALUTs LogicRegistersMemory Block(M10K/M20K) (6) (7)Arria 10RX1 1043 1504 1194 02 1575 2265 1815 04 2828 392

Figure 6-1: Multi-Stage Pipeline Register for SYSREF SignalFigure shows a two stages pipeline registers for the SYSREF signal.SYSREF at FPGA pinD Q D

Figure 6-2: Early RBD Release Opportunity for Latest Arrival Lane Within One Local Multi-FrameScenarioIn this example, the SYSREF pulse at rx_sysref p

Figure 6-3: Early RBD Release Opportunity for Latest Arrival Lane Across Two Local Multi-FramesScenarioIn this example, the RBD count varies from 7 to

Figure 6-4: Selecting Legal RBD Offset ValueFirst LMFC boundaryFree running LMFC counter 0 1 2345 60 1 2 3 4 5 6 7K K KK K K K KEarliest arrival laneD

Figure 6-5: Selecting Legal LMFC Offset Value for RXSequence of events in the diagram:1. Due to trace length mismatch, SYSREF pulse arrives at the ADC

You should set a safe LMFC offset value to ensure deterministic latency from one power cycle to anotherpower cycle. In Figure 6-6, the illegal csr_lmf

Figure 6-7: Example of Reducing LMFC Phase Offset between TX and RX LMFC CounterSequence of events in the diagram:1. SYSREF pulse arrives at the FPGA

The SYSREF pipeline registers in the FPGA introduce additional latency to SYSREF when detected by theIP core. Therefore, you can use TX LMFC offset to

JESD204B IP Core Debug Guidelines72015.05.04UG-01142SubscribeSend FeedbackThis section lists some guidelines to assist you in debugging JESD204B link

Check these items:• Turn off the scrambler and descrambler options as needed.• Use single lane configuration and K = 32 value to isolate multiple lane

Getting Started32015.05.04UG-01142SubscribeSend FeedbackThe JESD204B IP core is part of the MegaCore IP Library distributed with the Quartus II softwa

Check these items:• Review the schematic and board layout file to determine the polarity of the physical pin connection.• Use assignment editor and pi

Measure the rxphy_clk or txphy_clk frequency by connecting the clock to the CLKOUT pin on theFPGA. The frequency should be the same as link clock freq

Figure 7-1: JESD204B Link InitializationThis is a SignalTap II image during the JESD204B link initialization. The JESD204B link has twotransceiver cha

Transport LayerVerify the RX transport layer operation using these signals in the altera_jesd204_transport_rx_top.sv:• jesd204_rx_dataout• jesd204_rx_

Related Information• AN 696: Using the JESD204B MegaCore Function in Arria V DevicesMore information about the performance and interoperability of the

Additional Information82015.05.04UG-01142SubscribeSend FeedbackAdditional information about the document and Altera.JESD204B IP Core Document Revision

Date Version ChangesDecember20142014.12.15• Updated the JESD204B IP Core FPGA Performance table with thedata rate range.• Updated the JESD204B IP Core

Date Version ChangesJune 2014 2014.06.30• Updated Figure 2-1 to show a typical system application.• Updated the list of core key features.• Updated th

Contact(39)Contact Method AddressNontechnicalsupportGeneral Email [email protected] licensing Email [email protected] Informatio

Installing and Licensing IP CoresThe Altera IP Library provides many useful IP core functions for your production use without purchasingan additional

Table 3-1: IP Core Upgrade StatusIP Core Status DescriptionIP Upgraded Your IP variation uses the lastest version of the IP core.IP Upgrade Optional

your project, along with instructions for upgrading each core. Click Project > Upgrade IPComponents to access this dialog box manually.2. To upgrad

IP Catalog and Parameter EditorThe Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize andintegrate IP cores

ContentsJESD204B IP Core Quick Reference...1-1About the JESD204B IP Core...

Figure 3-3: Quartus II IP CatalogSearch for installed IP coresDouble-click to customize, right-click for detailed informationShow IP only for target d

• specify the working directory for the project.• assign the project name.• designate the name of the top-level design entity.1. From the Windows Star

• Set user-defined IP identifier• Enable Control and Status Registers• Enable Prbs Soft Accumulators4. In the Jesd204b Configurations tab, select the

Generating the Testbench Simulation ModelTo generate the testbench simulation model, execute the generated script (gen_sim_verilog.tcl orgen_sim_vhdl.

Table 3-3: Simulation Run ScriptsSimulator File Directory ScriptModelSim-AlteraSE/AE<example_design_directory>/ip_sim/testbench/mentor run_alter

Programming an FPGA DeviceAfter successfully compiling your design, program the targeted Altera device with the Quartus IIProgrammer and verify the de

Figure 3-4: Example of Connecting JESD204B IP Core with Other Qsys Components in QsysFigure shows an example of how you can connect the IP core with o

Adding External Transceiver PLLThe JESD204B IP core variations that target an Arria 10 FPGA device require external transceiver PLLsfor compilation.JE

In the .sdc file for your project, make the following command changes:• Specify the PLL clock reference pin frequency using the create_clock command.•

Table 3-4: Example AOriginal clocknames in altera_jesd204.sdcUser design inputclock namesFrequency(MHz)Recommended SDC timing constrainttx_pll_ref_clk

Scrambler/Descrambler... 4-14SYNC_N Signa

Table 3-5: Example BOriginal clocknames in altera_jesd204.sdcUser design inputclock namesFrequency(MHz)Recommended SDC timing constrainttx_pll_ref_clk

Parameter Value DescriptionData Path• Receiver• Transmitter• DuplexSelect the operation modes. This selection enables or disablesthe receiver and tran

Parameter Value DescriptionBonding Mode• Bonded• Non-bondedSelect the bonding modes.• Bonded—select this option to minimize inter-lanes skewfor the tr

Parameter Value DescriptionEnable Control andStatus Registers (14)On, Off Turn on this option to enable soft registers for reading statussignals and w

Frames per multiframe(K)1–32 Set the number of frames per multiframe. This value isdependent on the value of F and is derived using thefollowing const

Related InformationPerformance and Resource Utilization on page 2-6JESD204B IP Core Component FilesThe following table describes the generated files a

Table 3-8: Preset Configurations for JESD204B IP Core TestbenchConfiguration Preset ValueJESD204B Wrapper Base and PHY (MAC and PHY)Data Path DuplexPL

Testbench Simulation FlowThe JESD204B testbench simulation flow:1. At the start, the system is under reset (all the components are in reset).2. After

JESD204B IP Core Functional Description42015.05.04UG-01142SubscribeSend FeedbackThe JESD204B IP core implements a transmitter (TX) and receiver (RX) b

Figure 4-1: Overview of the JESD204B IP Core Block DiagramRX DriverTX DriverDeserializerSerializerFrame/LaneAlignmentCharacterGenerationDescramblerScr

JESD204B IP Core Quick Reference12015.05.04UG-01142SubscribeSend FeedbackThe Altera® JESD204B MegaCore® function is a high-speed point-to-point serial

Figure 4-2: JESD204B IP Core TX and RX Datapath Block DiagramThe JESD204B IP core utilizes the Avalon-ST source and sink interfaces, with unidirection

Avalon-MM InterfaceThe Avalon-MM slave interface provides access to internal CSRs. The read and write data width is 32-bits(DWORD access). The Avalon-

• TX CSR—manages the configuration and status registers.• TX_CTL—manages the SYNC_N signal, state machine that controls the data link layer states, LM

Table 4-1: Link Configuration Data Transmitted in ILAS PhaseConfigura‐tion OctetBitsDescriptionMSB 6 5 4 3 2 1 LSB0 DID[7:0] DID = Device ID1 ADJCNT[3

Configura‐tion OctetBitsDescriptionMSB 6 5 4 3 2 1 LSB11 RES1[7:0] RES1 = Reserved. Set to 8'h0012 RES2[7:0] RES2 = Reserved. Set to 8'h0013

Character replacement for scrambled dataThe character replacement for scrambled data in the IP core follows these JESD204B specification rules:• At en

Figure 4-4: Receiver Data Path Block DiagramTransceiver (RX)Per DeviceRX FrameDeassemblyPer DeviceRX CSRPer DeviceRX CTLPer DeviceDescramblerData Link

will be /K28.0/. Similar to the JESD204 TX IP core, the csr_lane_sync_en is set to 1 by default, thus theRX core detects the /K/ character to /R/ char

The realignment rules for lane alignment are similar to frame alignment:• If two successive and valid /A/ characters are detected at the same position

Figure 4-5: Subclass 1 Deterministic Latency and Support for Programmable Release OpportunityK K K K K K K K K K K K K K K K K K K K K K K KKKR D DD D

Item DescriptionIP CoreInformationCore Features • Run-time configuration of parameters L,M, and F• Data rates up to 12.5 gigabits per second (Gbps)• S

OperationOperating ModesThe JESD204B IP core supports Subclass 0, 1, and 2 operating modes.Subclass 0The JESD204 IP core maintains a LMFC counter that

For the alignment of LMFC to the TX logic, the JESD204 TX IP core samples SYNC_N from the DACreceiver and reports the relative phase difference betwee

Figure 4-6: Subclass 0 — Combining the SYNC_N Signal for JESD204B TX IP CoreSYSREF Tied to0 for Subclass 0JESD204B IP CoreTXSYSREFSYNC_NDEV_SYNC_NMDEV

Figure 4-7: Subclass 1 — Combining the SYNC_N Signal for JESD204B TX IP CoreSYSREF (Subclass 1)SYSREFSYNC_NDEV_SYNC_NMDEV_SYNC_NSYSREFSYNC_NDEV_SYNC_N

There are two modes of entry for link reinitialization:• Hardware initiated link reinitialization:• For TX, the reception of SYNC_N for more than five

RX (Subclass 0)The JESD204B RX IP core drives and holds SYNC_N (dev_sync_n signal) low when it is in reset. Uponreset deassertion, the JESD204B RX IP

Clock Signal Formula DescriptionTX/RX Link Clock:txlink_clkrxlink_clkData rate/40 The timing reference for the JESD204B IP core.Thelink clock runs at

Clock Signal Formula DescriptionTX/RX PHY Clock:txphy_clkrxphy_clkData rate/40 The link clock generated from the transceiver serialor parallel clock f

Figure 4-8: JESD204B Subsystem Clock Diagram (For Arria V and Stratix V Devices)Clock Jitter CleanerConverter Device 2Converter Devicedevice_clockSYSR

The Altera PLL IP core should provide both the frame clock and link clock from the same PLL as thesetwo clocks are treated as synchronous in the desig

About the JESD204B IP Core22015.05.04UG-01142SubscribeSend FeedbackThe Altera JESD204B IP core is a high-speed point-to-point serial interface for dig

Related InformationClock Correlation on page 4-23Clock CorrelationThis section describes the clock correlation between the device clock, link clock, f

Related Information• Device Clock on page 4-20• Link Clock on page 4-21• Local Multi-Frame Clock on page 4-22Reset SchemeAll resets in the JESD204B IP

Reset Signal Associated Clock Descriptiontx_analogreset[L-1:0]rx_analogreset[L-1:0]Transceiver Native PHYAnalog ResetActive high reset controlled by t

The bring-up sequence:1. Ensure that the core PLL and transceiver PLL are out of reset first.If the Transceiver PHY Reset Controller and Transceiver R

TransmitterTable 4-5: Transmitter SignalsSignal Width Direction DescriptionClocks and Resetspll_ref_clk1 Input Transceiver reference clock signal. The

Signal Width Direction Descriptionpll_locked[] (22)L Output PLL locked signal for the hard transceiver.This signal is asserted to indicate that the TX

Signal Width Direction Descriptionreconfig_to_xcvr[]• (L+1)*70 ifbonding mode ="xN"• L*140 ifbonding mode =feedbackcompensationInput Reconfi

Signal Width Direction Descriptionreconfig_avmm_writedata[]32 InputThe input data.This signal is only available if you enabledynamic reconfiguration f

Signal Width Direction Descriptionjesd204_tx_link_valid1 Input Indicates whether the data from the transportlayer is valid or invalid. The Avalon-ST s

Signal Width Direction Descriptionjesd204_tx_avs_chipselect1 Input When this signal is present, the slave portignores all Avalon-MM signals unless thi

Figure 2-1: Typical System Application for JESD204B IP CoreThe JESD204B IP core utilizes the Avalon-ST source and sink interfaces, with unidirectional

Signal Width Direction Descriptionsync_n1 Input Indicates SYNC_N from the converter device orreceiver. This is an active low signal and isasserted 0 t

Signal Width Direction Descriptioncsr_l[]5 Output Indicates the number of active lanes for thelink. The transport layer can use this signal asa run-ti

Signal Width Direction Descriptioncsr_tx_testmode[]4 Output Indicates the address space that is reserved forDLL testing within the JESD204B IP core.•

ReceiverTable 4-6: Receiver SignalsSignal Width Direction DescriptionClocks and Resetspll_ref_clk1 Input Transceiver reference clock signal.rxlink_clk

Signal Width Direction Descriptionreconfig_to_xcvr[]L*70 Input Dynamic reconfiguration input for the hardtransceiver.This signal is only applicable fo

Signal Width Direction Descriptionreconfig_avmm_readdata[]32 OutputThe output data.This signal is only available if you enable dynamicreconfiguration

Signal Width Direction Descriptionjesd204_rx_avs_clk1 Input The Avalon-MM interface clock signal. This clockis asynchronous to all the functional cloc

Signal Width Direction Descriptionjesd204_rx_avs_waitrequest1 Output This signal is asserted by the Avalon-MM slave toindicate that it is unable to re

Signal Width Direction Descriptionalldev_lane_aligned1 Input Aligns all lanes for this device.For multidevice synchronization, multiplex all thedev_la

Signal Width Direction Descriptioncsr_cf[]5 Output Indicates the number of control words per frameclock period per link. The transport layer can useth

Datapath ModesThe JESD204B IP core supports TX-only, RX-only, and Duplex (TX and RX) mode. The IP core is aunidirectional protocol where interfacing t

RegistersThe JESD204B IP core supports a basic one clock cycle transaction bus. There is no support for burstmode and wait-state feature (the avs_wait

Access Type DefinitionRW1S• Software reads shall return the current bit value.• Software writes 0 shall have no effect.• Software writes 1 shall set t

JESD204B IP Core Design Guidelines52015.05.04UG-01142SubscribeSend FeedbackThis section describes the design example included with the IP core and som

Figure 5-1: Design Example Block DiagramPatternGeneratorSampleMapper(2)(3)(3)(2)(3)(6)PCSSerPCSDesDeassembler(TransportLayer)Avalon-ST32 BitRX BaseCor

6. You can enable internal serial loopback by setting the rx_seriallpbken input signal. You candynamically toggle this input signal. When toggled to 1

Related Information• Clocking Scheme on page 4-18More information about the JESD204B IP core clocks.PLL ReconfigurationThe PLL reconfiguration utilize

requires a read-modify-write operation (read first, then write), in such a way that it modifies only theappropriate bits in a register and not changin

For Arria 10 devices, the only Avalon-MM operation is a direct write to the transceiver register throughthe reconfig_avmm_* interface at the JESD204B

length of the shift register. Polynomial notation—which the polynomial order corresponds to the lengthof the shift register and the period of PRBS—pro

that the input data is valid. The checker flags an error when it finds any single mismatch between theexpected data and input data.Ramp Wave CheckerTh

JESD204B IP Core ConfigurationTable 2-1: JESD204B IP Core ConfigurationSymbol Description ValueL Number of lanes per converter device 1-8M Number of c

do not have this capability in the transport layer. If you needs to change any of these parameters, youmust recompile the system.You are advised to co

Figure 5-2: Mapping of Data Bit and Content Across Various Interfaces (LMF = 112, N = 12, N' = 16, S =1, T represents the tail bits).012345678910

Figure 5-3: TX Path Assembler Block DiagramTail BitsPaddingAssembling MultiplexingTX Controljesd204_tx_link_datain[(L*32)-1:0]Configuration Register S

Parameter Description ValueF1_FRAMECLK_DIVOnly applies to cases where F=1.The divider ratio on the frame_clk. The assembler always use thepost-divided

Signal Clock Domain Direction Descriptiontxlink_rst_n txlink_clkInputReset for the TX link clock domain logic in theassembler. This reset is an active

Signal Clock Domain Direction Descriptionjesd204_tx_link_datain[(L*32)-1:0]txlink_clk Output Indicates transmitted data from the transportlayer to the

Signal Clock Domain Direction Descriptioncsr_l[4:0] (31)mgmt_clkInputIndicates the number of active lanes for the link.This 5-bit bus represents the L

Signal Clock Domain Direction Descriptioncsr_n[4:0] (31)mgmt_clkInputIndicates the converter resolution. This 5-bit busrepresents the N value in zero-

Figure 5-4: TX Operation BehaviorThis figure shows the data transmission for a system configuration of LMF = 112, N = N' = 16, S = 1.Operation:•

Figure 5-5: TX Data TransmissionJunk datain Valid DataJunk Sampled Data Valid Datatxframe_clktxlink_clktxframe_rst_ntxlink_rst_njesd204_tx_datavalidTL