Altera Avalon Verification IP Suite Manuel d'utilisateur télécharger pdf (Page 214)

Running the Verilog HDL Testbench for the Two Avalon-MM Masters and Slaves

1. Unzip ug_avalon_verification.zip to a working directory.

2. Open <working_dir>/avlm_avls_2x2.qsys.

3. Complete the following steps to generate the testbench:

a. On the Generate menu, select Generate HDL.

b. Specify the parameters shown in the following table:

Table 17-2: Generation Parameters

ValueParameter

Synthesis

Leave this option offCreate HDL design files for synthesis

Leave this option offCreate timing and resource estimates for third-party

EDA synthesis tools

Leave this option onCreate block symbol file (.bsf)

Simulation

VerilogCreate simulation model

Leave this option offAllow mixed-language simulation

Output Directory

<working_dir>/avlm_avls_2x2Path

c. Click Generate.

The Qsys Generate window displays informational messages as it generates the testbench.

d. Close the Generate window.

4. Start the ModelSim simulator.

5. To run the simulation, type the following command in your working directory:

do run_simulation.tcl

This command compiles all the required HDL files, elaborates, and runs the simulation.

Avalon-MM Verilog HDL and VHDL Testbenches

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Altera Avalon Verification IP Suite Manuel d'utilisateur Page 214