Altera High-Speed Development Kit, Stratix GX Edition Manuel d'utilisateur télécharger pdf (Page 84)

7–2 Quartus II Version 3.0 Altera Corporation

Standard Tests High-Speed Development Kit, Stratix GX Edition User Guide

An enhanced PLL clocks these test designs. The PLL uses the 33-MHz

signal from the on-board crystal oscillator as the reference clock. The PLL

generates three internal clocks that are used in three different parts of the

circuit:

■ One clock is multiplied by one to generate a 33-MHz clock, which

clocks all of the modules responsible for testing the pushbutton

switches, LEDs, 7-segment displays, and dipswitches.

■ One clock is multiplied by 6 to generate a 200-MHz clock, which

clocks the data generators creating the data that is sent to the 20-pin

headers and the Mictor connector.

■ One clock is multiplied by 12 to generate a 400-MHz clock, which is

divided by 2 to generate 200-MHz clocks as reference clocks for the

Mictor connector.

User I/O Test Functional Description

Figure 7–1 shows the user I/O logic diagram for the Stratix GX and

Stratix devices.

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Altera High-Speed Development Kit, Stratix GX Edition Manuel d'utilisateur Page 84