NCO IP CoreUser GuideSubscribeSend FeedbackUG-NCO2014.12.15101 Innovation DriveSan Jose, CA 95134www.altera.com

Use the following features to help you quickly locate and select an IP core:• Filter IP Catalog to Show IP for active device family or Show IP for all

1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.The parameter editor appears.2. Specify a t

Figure 2-3: IP Parameter EditorView IP portand parameter detailsApply preset parameters forspecific applicationsSpecify your IP variation nameand targ

Figure 2-4: IP Core Generated Files<your_testbench>_tb.csv<your_testbench>_tb.spd<your_ip>.cmp - VHDL component declaration file<

File Name Description<my_ip>.cmp The VHDL Component Declaration (.cmp) file is a text file thatcontains local generic and port definitions that

File Name Description<my_ip>.svdAllows HPS System Debug tools to view the register maps ofperipherals connected to HPS within a Qsys system.Duri

Figure 2-5: Simulation in Quartus II Design FlowPost-fit timing simulation netlist Post-fit timing simulation (3)Post-fit functional simulation net

Related InformationUsing MegaCore Functions chapter in the DSP Builder Handbook.2-10DSP Builder Design FlowUG-NCO2014.12.15Altera CorporationNCO IP Co

NCO IP Core Functional Description32014.12.15UG-NCOSubscribeSend FeedbackFigure 3-1: NCO Block DiagramsinecosinefINCfFMInternalDitherfDITHWaveformGene

where M is the accumulator precision and fclk is the clock frequencyThe minimum possible output frequency waveform is generated for the case where ϕin

ContentsAbout the NCO IP Core... 1-1Altera DSP IP Core Features...

Table 3-1: Derivation of Output ValuesPosition in UnitCircleRange for Phase x sin(x) cos(x)1 0 <= x < π/4 sin(x) cos(x)2 π/4 <= x < π/2 co

only. Therefore, the algorithm can be implemented efficiently by a series of simple binary shift andadditions/subtractions.In an NCO, the CORDIC algor

Table 3-2: Architecture ComparisonArchitecture AdvantagesLargeROMGood for high speed and when a large quantity of internalmemory is available. Gives t

Figure 3-4: Frequency Hopping Block DiagramNumericallyControlledOscillatorfcos_oout_validAvalon-MMInterfaceclkreset_nreset_naddresswrite_sigincrementf

Frequency ModulationYou can add an optional frequency modulator to your custom NCO variation. You can use the frequencymodulator to vary the oscillato

Parameter Value DescriptionNumber of Bands 1–16 Select a number of bands greater than 1 to enablefrequency hopping. Frequency hopping is notsupported

Parameter Value DescriptionReal OutputFrequency— Displays the calculated value of the real outputfrequency.Related Information• Frequency Modulation o

and valid signals. Avalon-ST interfaces can also support more complex protocols for burst and packettransfers with packets interleaved across multiple

NCO IP Core Timing DiagramsFigure 3-5: Single-Cycle Per Output Timing Diagramclkclkenphi_inc_ireset_nfsin_0fcos_0out_valid429496730 -3 2057 41... 61..

After the clock enable is asserted, the oscillator outputs sinusoidal samples at a rate of one sample per Nclock cycles, where N is the magnitude prec

Opening the NCO Multichannel Design Example...4-4Document Revision Hist

The output values Sk and Ck corresponding to channels 1 through (M-1) are output sequentially by theNCO. The outputs are interleaved so that a new out

NCO Multichannel Design Example42014.12.15UG-NCOSubscribeSend FeedbackOften in a system where the clock frequency of the design is much higher than th

The following directories contain separate top-level design files (named multichannel_example.v andmultichannel_example.vhd) for Verilog HDL and VHDL

To meet the specification, the design uses the following parameters:• Multiplier-based algorithm. By using the dedicated multiplier circuitry in Strat

The ModelSim simulation script generates signals with different frequencies and phases in four separatechannels. .Table 4-1: ModelSim Simulation Map P

Document Revision History52014.12.15UG-NCOSubscribeSend FeedbackNCO IP User Guide revision historyDate Version Changes Made2014.12.15 14.1• Added full

About the NCO IP Core12014.12.15UG-NCOSubscribeSend FeedbackThe Altera® NCO IP core generates numerically controlled oscillators (NCOs) customized for

• Avalon® Streaming (Avalon-ST) interfaces• DSP Builder ready• Testbenches to verify the IP core• IP functional simulation models for use in Altera-su

Device Family SupportMAX® 10 FPGA FinalStratix® IV GT FinalStratix IV GX/E FinalStratix V FinalOther device families No supportNCO IP Core MegaCore Ve

Altera verifies that the current version of the Quartus II software compiles the previous version of each IPcore. Altera does not verify that the Quar

NCO IP Core Getting Started22014.12.15UG-NCOSubscribeSend Feedback1.Installing and Licensing IP CoresThe Altera IP Library provides many useful IP cor

• Simulate the behavior of a licensed IP core in your system.• Verify the functionality, size, and speed of the IP core quickly and easily.• Generate