Altera DDR Timing Wizard Manuel d'utilisateur télécharger pdf (Page 90)

3–30 Altera Corporation

DDR Timing Wizard User Guide November 2007

Timing Closure Process

1 The MegaWizard inverts the address/command clock in a

lower-level file of the controller when the Clock

address/command output registers on the negative edge

option is on. Instead, you can manually add 180

° phase shift in

the altpll MegaWizard for easier tracking.

To use a dedicated PLL output for the address and command clock,

enable the c3 output of the system PLL and connect this output to

addrcmd_clk in the <variation_name> instantiation. The system PLL

instantiation code in the <project_name>.v/vhd file looks similar to the

example below:

ddr_pll_stratixii g_stratixpll_ddr_pll_inst

(

.c0 (clk),

.c1 (write_clk),

.c2 (dedicated_resynch_or_capture_clk),

.c3 (dedicated_addrcmd_clk),

.inclk0 (clock_source)

);

The MegaWizard uses an input PLL clock that is of the same frequency as

the memory interface. You need to change this in the altpll

MegaWizard for the ddr_pll_stratixii module.

In the <variation_name> instantiation in the <project_name>.v/file, change:

.addrcmd_clk (clk),

to:

.addrcmd_clk (dedicated_addrcmd_clk),

w Since the design example is modified, make sure you uncheck

the Update the design example file that instantiates the

controller variation option in the Project Setting page the next

time you invoke the DDR2 SDRAM Controller MegaWizard.

You must then configure the phase shift for the output using the altpll

MegaWizard Plug-In Manager.

Moving the Data Path Registers Closer to the Pins

In some cases, you may need to change the DQ pin locations instead of

using the default MegaWizard-generated locations. Since the

MegaWizard also places the resynchronization registers based on the

default DQ pin locations, you may need to change the resynchronization

registers also to get the optimal timing margins.

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Altera DDR Timing Wizard Manuel d'utilisateur Page 90