Altera DDR Timing Wizard Manuel d'utilisateur Page 13
- Page / 92
- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Altera Corporation 2–1
November 2007
2. Getting Started
System and
Software
Requirements
The instructions in this section require Quartus II software version 7.2 or
higher. DTW and the dtw_timing_analysis.tcl script can be found in the
Quartus II installation directory. You can either run the script from that
directory or copy the script to your project directory.
1 If you use the default installation directory, the DTW and
dtw_timing_analysis.tcl script are available in the
c:\altera\<version>\quartus\common\tcl\apps\
gui\dtw directory.
Design Flow
The design flow when creating a system with external memory interfaces
is as follows:
1. Create a memory interface PHY with Altera’s legacy memory
controller MegaWizard.
f For more information about how to create a memory
controller, refer to the DDR & DDR2 SDRAM Controller
Compiler User Guide, QDRII SRAM Controller MegaCore
®
Function User Guide, and RLDRAM II Controller MegaCore
Function User Guide. Follow the instructions up to
generating the core, but do not compile the design yet.
f To create an example design, follow the Instantiate PHY
and Controller in a Quartus II Project step of the
"Example Walkthrough for 267-MHz DDR2 SDRAM
Interface using the Legacy PHY" section in AN328:
Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and
Arria GX Devices.
If you are not using the Altera memory controller, remove the
encrypted controller produced by the legacy controller MegaWizard
and connect the Altera-recommended data path from the legacy
controller MegaWizard with your memory controller.
2. Run the auto_add_ddr_constraints.tcl script produced by the
legacy controller MegaWizard for pin location, I/O standard,
output pin load, and register placement assignments for the
resynchronization and postamble registers in DDR2/DDR SDRAM
interfaces.
- DDR Timing Wizard 1
- Table of Contents 3
- November 2007 4
- About this User Guide 5
- Typographic 6
- Conventions 6
- 1. About the DDR Timing 7
- Device Family 8
- 1–4 Altera Corporation 10
- Introduction 10
- Altera Corporation 1–5 11
- About the DDR Timing Wizard 11
- Note to Figure 1–1: 11
- Features 12
- 2. Getting Started 13
- Design Flow 14
- 2–2 Altera Corporation 14
- Altera Corporation 2–3 15
- Getting Started 15
- 2–4 Altera Corporation 16
- Launching the 17
- DDR Timing 17
- Entering and 18
- Editing Inputs to 18
- Recommended Data Path 19
- 2–8 Altera Corporation 20
- Altera Corporation 2–9 21
- 2–10 Altera Corporation 22
- Altera Corporation 2–11 23
- 2–12 Altera Corporation 24
- Altera Corporation 2–13 25
- Synchronous Systems 26
- Altera Corporation 2–15 27
- (Figure 2–10) 28
- Altera Corporation 2–17 29
- 2–18 Altera Corporation 30
- Analysis & Synthesis 31
- 2–20 Altera Corporation 32
- Altera Corporation 2–21 33
- 2–22 Altera Corporation 34
- Click Next 35
- 2–24 Altera Corporation 36
- Altera Corporation 2–25 37
- 2–26 Altera Corporation 38
- Altera Corporation 2–27 39
- 2–28 Altera Corporation 40
- Altera Corporation 2–29 41
- Altera Corporation 2–31 43
- 200 MHz) 44
- Altera Corporation 2–33 45
- 2–34 Altera Corporation 46
- Altera Corporation 2–35 47
- 2–36 Altera Corporation 48
- Altera Corporation 2–37 49
- 2–38 Altera Corporation 50
- Altera Corporation 2–39 51
- 2–40 Altera Corporation 52
- Altera Corporation 2–41 53
- 2–42 Altera Corporation 54
- Altera Corporation 2–43 55
- Click Finish 56
- Altera Corporation 2–45 57
- DTW Limitations 58
- 2–48 Altera Corporation 60
- 3. Using the 61
- 3–2 Altera Corporation 62
- -dwz_file <value> 63
- -? or -help 63
- -after_iptb <value> 64
- -auto_adjust_cycles 64
- -extract_tcos <value> 64
- *auk_ddr_datapath 65
- *auk_qdrii_sram_datapath 65
- *auk_rldramii_datapath 65
- -stop_after <value> 66
- -vwf_file_name <value> 66
- -write_side 66
- Altera Corporation 3–7 67
- ■ Timing Summary 67
- Altera Corporation 3–9 69
- ■ Recommended Settings 69
- Timing Closure 72
- Altera Corporation 3–13 73
- Note to Figure 3–6: 73
- DDR2/DDR SDRAM Interfaces 74
- QDRII+/QDRII SRAM Interfaces 74
- RLDRAM II Interfaces 75
- 3–16 Altera Corporation 76
- Timing Closure Process 76
- Altera Corporation 3–17 77
- Analyzer 78
- Altera Corporation 3–19 79
- 3–20 Altera Corporation 80
- Altera Corporation 3–21 81
- 3–22 Altera Corporation 82
- Changing Clock Phase Shift 83
- 3–24 Altera Corporation 84
- Altera Corporation 3–25 85
- Changing Clock Cycles 87
- 3–28 Altera Corporation 88
- Altera Corporation 3–29 89
- 3–30 Altera Corporation 90
- ° phase shift in 90
- Altera Corporation 3–31 91
- Conclusion 92
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