Altera DDR Timing Wizard Manuel d'utilisateur télécharger pdf (Page 88)

3–28 Altera Corporation

DDR Timing Wizard User Guide November 2007

Timing Closure Process

In the DTW, however, if you create a 2-PLL mode memory interface,

DTW needs two clock cycle selections each for resynchronization and

postamble paths. DTW uses the clock cycle selections from the legacy

controller MegaWizard for one and estimates the clock cycles for the

other one. See Figure 2–21 on page 29 and figure Figure 2–23 on page 33

for the relationship of the clock cycles in the legacy memory controller

MegaWizard and the DTW.

Because of this relationship, depending on which clock cycle the

dtw_timing_analysis.tcl asks you to adjust, you need to either change the

clock cycle in the legacy memory controller MegaWizard or in the DTW.

If the Recommended Settings panel asks you to change the clock cycle in

both MegaWizard and DTW, change the clock cycle in DTW, synthesize

the design, and re-import the memory settings into the DTW. More often

than not, DTW will be able to recalculate the other clock cycle selection

and pick the correct one. You should, however, ensure that they are

correct.

Changing the Address/Command Clock Connection and Phase

Shift

This is applicable to DDR2/DDR SDRAM interfaces only. To change the

address/command clock in RLDRAM II interfaces, refer to the

“Changing Clock Phase Shift” on page 3–23.

In order to use a dedicated PLL output clock for the address/command

clock, you need to enable the Insert extra pipeline registers in the

datapath option and disable the Clock address/command output

registers on the negative edge option, as shown in Figure 3–15.

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Altera DDR Timing Wizard Manuel d'utilisateur Page 88