Altera DDR Timing Wizard Manuel d'utilisateur Page 16
- Page / 92
- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
2–4 Altera Corporation
DDR Timing Wizard User Guide November 2007
Design Flow
standard as the CK/CK# pins, and are placed on the same side
as the DQS/DQ pins.
● Assign pin location, I/O standard, and output pin load
constraints for clock_source, feedback input pins, and
address and command pins.
● For RLDRAM II memory interfaces created in Quartus II
version 7.2 and higher, add the
<variation_name>_controller.sdc file to the project
● For QDRII+/QDRII SRAM memory interfaces using TimeQuest
Timing Analyzer, convert the setup_relationship and
hold_relationship MegaWizard-generated constraints to
SDC constraints. The setup_relationship and
hold_relationship assignment can be directly converted to
set_max_delay and set_min_delay assignments, as shown
in the below example:
set_max_delay -0.2 -from * -to <resync_registers*>
set_min_delay -1.6 -from * -to <resync_registers*>
5. Compile the design.
6. Check the timing analysis results.
After completing a DTW design compilation, refer to Chapter 3,
Using the dtw_timing_analysis.tcl Script for information about
analyzing the memory interfaces.
If problem paths are reported, locate and fix them to maximize setup
and hold slack. For example, you can:
● Adjust PLL clock phases with the legacy controller or the
altpll MegaWizard.
1 Note that some clock phases can only be changed in the
legacy controller MegaWizard, especially for shared PLL
outputs. For example, if your postamble clock was set to 90°
initially, but you want to change it to use either a dedicated
clock or a 180° phase shift.
● Insert or remove intermediate resynchronization and/or
postamble registers in the legacy controller MegaWizard.
- DDR Timing Wizard 1
- Table of Contents 3
- November 2007 4
- About this User Guide 5
- Typographic 6
- Conventions 6
- 1. About the DDR Timing 7
- Device Family 8
- 1–4 Altera Corporation 10
- Introduction 10
- Altera Corporation 1–5 11
- About the DDR Timing Wizard 11
- Note to Figure 1–1: 11
- Features 12
- 2. Getting Started 13
- Design Flow 14
- 2–2 Altera Corporation 14
- Altera Corporation 2–3 15
- Getting Started 15
- 2–4 Altera Corporation 16
- Launching the 17
- DDR Timing 17
- Entering and 18
- Editing Inputs to 18
- Recommended Data Path 19
- 2–8 Altera Corporation 20
- Altera Corporation 2–9 21
- 2–10 Altera Corporation 22
- Altera Corporation 2–11 23
- 2–12 Altera Corporation 24
- Altera Corporation 2–13 25
- Synchronous Systems 26
- Altera Corporation 2–15 27
- (Figure 2–10) 28
- Altera Corporation 2–17 29
- 2–18 Altera Corporation 30
- Analysis & Synthesis 31
- 2–20 Altera Corporation 32
- Altera Corporation 2–21 33
- 2–22 Altera Corporation 34
- Click Next 35
- 2–24 Altera Corporation 36
- Altera Corporation 2–25 37
- 2–26 Altera Corporation 38
- Altera Corporation 2–27 39
- 2–28 Altera Corporation 40
- Altera Corporation 2–29 41
- Altera Corporation 2–31 43
- 200 MHz) 44
- Altera Corporation 2–33 45
- 2–34 Altera Corporation 46
- Altera Corporation 2–35 47
- 2–36 Altera Corporation 48
- Altera Corporation 2–37 49
- 2–38 Altera Corporation 50
- Altera Corporation 2–39 51
- 2–40 Altera Corporation 52
- Altera Corporation 2–41 53
- 2–42 Altera Corporation 54
- Altera Corporation 2–43 55
- Click Finish 56
- Altera Corporation 2–45 57
- DTW Limitations 58
- 2–48 Altera Corporation 60
- 3. Using the 61
- 3–2 Altera Corporation 62
- -dwz_file <value> 63
- -? or -help 63
- -after_iptb <value> 64
- -auto_adjust_cycles 64
- -extract_tcos <value> 64
- *auk_ddr_datapath 65
- *auk_qdrii_sram_datapath 65
- *auk_rldramii_datapath 65
- -stop_after <value> 66
- -vwf_file_name <value> 66
- -write_side 66
- Altera Corporation 3–7 67
- ■ Timing Summary 67
- Altera Corporation 3–9 69
- ■ Recommended Settings 69
- Timing Closure 72
- Altera Corporation 3–13 73
- Note to Figure 3–6: 73
- DDR2/DDR SDRAM Interfaces 74
- QDRII+/QDRII SRAM Interfaces 74
- RLDRAM II Interfaces 75
- 3–16 Altera Corporation 76
- Timing Closure Process 76
- Altera Corporation 3–17 77
- Analyzer 78
- Altera Corporation 3–19 79
- 3–20 Altera Corporation 80
- Altera Corporation 3–21 81
- 3–22 Altera Corporation 82
- Changing Clock Phase Shift 83
- 3–24 Altera Corporation 84
- Altera Corporation 3–25 85
- Changing Clock Cycles 87
- 3–28 Altera Corporation 88
- Altera Corporation 3–29 89
- 3–30 Altera Corporation 90
- ° phase shift in 90
- Altera Corporation 3–31 91
- Conclusion 92
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