Altera DDR Timing Wizard Manuel d'utilisateur télécharger pdf (Page 38)

2–26 Altera Corporation

DDR Timing Wizard User Guide November 2007

Entering and Editing Inputs to the DTW

1 The default TimeQuest Timing Analyzer clocking names

are shown in Figure 2–19. If you are using Classic Timing

Analyzer, the default clocking names for the system PLL

are:

ddr_pll_stratixii:g_stratixpll_ddr_pll_inst

|altpll:altpll_component|_clkn

where n denotes the PLL output counter number.

Clicking on a field in this page highlights the location of that field in

the design schematic in the bottom of the page. For example, if you

click on the resync_cycle field as shown in Figure 2–20, the path

from the system PLL to the Resync DFF1 is highlighted to show

where the resync_cycle information is used. The DTW shows a

different schematic if the interface is using 1-PLL mode.

1 You can use the highlights as a guide when you must enter

each field manually. The design schematic varies

depending on the interface mode, whether you are using

DQS, or whether you are using 2-PLL (with the fedback

PLL) or 1-PLL mode. This example design uses DQS with

2-PLL implementation.

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Altera DDR Timing Wizard Manuel d'utilisateur Page 38