Altera DDR Timing Wizard Manuel d'utilisateur Page 66
- Page / 92
- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
3–6 Altera Corporation
DDR Timing Wizard User Guide November 2007
Introduction
4. Open the Compilation Report panel by clicking on Compilation
Report under the Processing menu. If the Compilation Report
panel is open, you have to close it and reopen it.
The dtw_timing_analysis.tcl script appends its result onto the
Compilation Report, and is automatically displayed after refreshing
the Compilation Report panel.
The dtw_timing_analysis.tcl Script Results
The script result is added at the bottom of the compilation result as
Memory Interface Timing with the name of the controller and .dwz file
in parentheses under that folder, and shows the script result with my_core
(ddr_settings.dwz), because the controller’s name is my_core and the
.dwz file name used to constrain the memory interface timing is called
ddr_settings.dwz, as shown in Figure 3–2.
-stop_after <value>
Any integer Indicates the maximum number of
iterations when using the
-auto_adjust_cycles switch to
prevent infinite iterations. The default
value is 5.
No
-vwf_file_name <value>
A .vwf file name Creates a waveform showing the
interface timing margin in a .vwf
format.
No
-write_side
● tanrpt
● tq
● skip
● auto
Tells the script whether you want to
use Classic or TimeQuest Timing
Analyzer for the write side timing
analysis. You also have the option to
skip write timing analysis. The default
is TimeQuest Timing Analyzer,
regardless of what timing analyzer
was used in the design. Classic timing
analyzer is not recommended for write
timing analysis.
No
Notes to Ta b le 3 –1 :
(1) Fedback clock in this implementation is used for read capture, not for resynchronization.
(2) RLDRAM II and QDRII+/QDRII SRAM interfaces do not require resynchronization clocks, as the Altera IP MegaCore
functions use a FIFO to resynchronize data to system clock.
Table 3–1. Switches in the dtw_timing_analysis.tcl Script (Part 4 of 4) Notes (1), (2)
Switch Possible Value Description Required
- DDR Timing Wizard 1
- Table of Contents 3
- November 2007 4
- About this User Guide 5
- Typographic 6
- Conventions 6
- 1. About the DDR Timing 7
- Device Family 8
- 1–4 Altera Corporation 10
- Introduction 10
- Altera Corporation 1–5 11
- About the DDR Timing Wizard 11
- Note to Figure 1–1: 11
- Features 12
- 2. Getting Started 13
- Design Flow 14
- 2–2 Altera Corporation 14
- Altera Corporation 2–3 15
- Getting Started 15
- 2–4 Altera Corporation 16
- Launching the 17
- DDR Timing 17
- Entering and 18
- Editing Inputs to 18
- Recommended Data Path 19
- 2–8 Altera Corporation 20
- Altera Corporation 2–9 21
- 2–10 Altera Corporation 22
- Altera Corporation 2–11 23
- 2–12 Altera Corporation 24
- Altera Corporation 2–13 25
- Synchronous Systems 26
- Altera Corporation 2–15 27
- (Figure 2–10) 28
- Altera Corporation 2–17 29
- 2–18 Altera Corporation 30
- Analysis & Synthesis 31
- 2–20 Altera Corporation 32
- Altera Corporation 2–21 33
- 2–22 Altera Corporation 34
- Click Next 35
- 2–24 Altera Corporation 36
- Altera Corporation 2–25 37
- 2–26 Altera Corporation 38
- Altera Corporation 2–27 39
- 2–28 Altera Corporation 40
- Altera Corporation 2–29 41
- Altera Corporation 2–31 43
- 200 MHz) 44
- Altera Corporation 2–33 45
- 2–34 Altera Corporation 46
- Altera Corporation 2–35 47
- 2–36 Altera Corporation 48
- Altera Corporation 2–37 49
- 2–38 Altera Corporation 50
- Altera Corporation 2–39 51
- 2–40 Altera Corporation 52
- Altera Corporation 2–41 53
- 2–42 Altera Corporation 54
- Altera Corporation 2–43 55
- Click Finish 56
- Altera Corporation 2–45 57
- DTW Limitations 58
- 2–48 Altera Corporation 60
- 3. Using the 61
- 3–2 Altera Corporation 62
- -dwz_file <value> 63
- -? or -help 63
- -after_iptb <value> 64
- -auto_adjust_cycles 64
- -extract_tcos <value> 64
- *auk_ddr_datapath 65
- *auk_qdrii_sram_datapath 65
- *auk_rldramii_datapath 65
- -stop_after <value> 66
- -vwf_file_name <value> 66
- -write_side 66
- Altera Corporation 3–7 67
- ■ Timing Summary 67
- Altera Corporation 3–9 69
- ■ Recommended Settings 69
- Timing Closure 72
- Altera Corporation 3–13 73
- Note to Figure 3–6: 73
- DDR2/DDR SDRAM Interfaces 74
- QDRII+/QDRII SRAM Interfaces 74
- RLDRAM II Interfaces 75
- 3–16 Altera Corporation 76
- Timing Closure Process 76
- Altera Corporation 3–17 77
- Analyzer 78
- Altera Corporation 3–19 79
- 3–20 Altera Corporation 80
- Altera Corporation 3–21 81
- 3–22 Altera Corporation 82
- Changing Clock Phase Shift 83
- 3–24 Altera Corporation 84
- Altera Corporation 3–25 85
- Changing Clock Cycles 87
- 3–28 Altera Corporation 88
- Altera Corporation 3–29 89
- 3–30 Altera Corporation 90
- ° phase shift in 90
- Altera Corporation 3–31 91
- Conclusion 92
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