Altera DDR Timing Wizard Manuel d'utilisateur Page 64
- Page / 92
- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
3–4 Altera Corporation
DDR Timing Wizard User Guide November 2007
Introduction
-after_iptb <value>
import Instructs the script to analyze and
elaborate the design and import the
design settings into DTW. Use this
switch after making changes in the
PLL or memory controller
MegaWizard. You must create a
memory controller using the
MegaWizard to use this switch. The
default value for this switch is none,
which means that the script does not
import any settings.
No
import_and_compile Allows the script to compile the design,
extract the timing margins, and
recommend ideal clock cycles and
phase shift settings after performing
the import part of the script (see
above).
No
-auto_adjust_cycles
None Allows the script to adjust the clock
cycles if the current absolute timing
margin is bigger than one clock period.
This is to set the design properly so
that the margin shown is accurate and
realistic. You have to add this switch if
you want the script to adjust the clock
cycles automatically. The correct clock
cycle will updated the .dwz file
automatically.
No
-extract_tcos <value>
● yes
● no
● auto
● prompt
Indicates whether you want the script
to extract the design t
CO
s and import
them into DTW when the design t
CO
s
do not match what are currently in
DTW. The default setting is auto,
which compares the t
CO
s and imports
the design t
CO
s if they do not match the
current DTW information. You can
extract t
CO
s at every run (yes) or
ignore the t
CO
mismatch (no). When
the value is prompt, the script exits if
the design t
CO
s do not match the DTW
information. Extracting t
CO
s may take
a while if you have a big design.
No
-debug
None Lists debug messages. No
Table 3–1. Switches in the dtw_timing_analysis.tcl Script (Part 2 of 4) Notes (1), (2)
Switch Possible Value Description Required
- DDR Timing Wizard 1
- Table of Contents 3
- November 2007 4
- About this User Guide 5
- Typographic 6
- Conventions 6
- 1. About the DDR Timing 7
- Device Family 8
- 1–4 Altera Corporation 10
- Introduction 10
- Altera Corporation 1–5 11
- About the DDR Timing Wizard 11
- Note to Figure 1–1: 11
- Features 12
- 2. Getting Started 13
- Design Flow 14
- 2–2 Altera Corporation 14
- Altera Corporation 2–3 15
- Getting Started 15
- 2–4 Altera Corporation 16
- Launching the 17
- DDR Timing 17
- Entering and 18
- Editing Inputs to 18
- Recommended Data Path 19
- 2–8 Altera Corporation 20
- Altera Corporation 2–9 21
- 2–10 Altera Corporation 22
- Altera Corporation 2–11 23
- 2–12 Altera Corporation 24
- Altera Corporation 2–13 25
- Synchronous Systems 26
- Altera Corporation 2–15 27
- (Figure 2–10) 28
- Altera Corporation 2–17 29
- 2–18 Altera Corporation 30
- Analysis & Synthesis 31
- 2–20 Altera Corporation 32
- Altera Corporation 2–21 33
- 2–22 Altera Corporation 34
- Click Next 35
- 2–24 Altera Corporation 36
- Altera Corporation 2–25 37
- 2–26 Altera Corporation 38
- Altera Corporation 2–27 39
- 2–28 Altera Corporation 40
- Altera Corporation 2–29 41
- Altera Corporation 2–31 43
- 200 MHz) 44
- Altera Corporation 2–33 45
- 2–34 Altera Corporation 46
- Altera Corporation 2–35 47
- 2–36 Altera Corporation 48
- Altera Corporation 2–37 49
- 2–38 Altera Corporation 50
- Altera Corporation 2–39 51
- 2–40 Altera Corporation 52
- Altera Corporation 2–41 53
- 2–42 Altera Corporation 54
- Altera Corporation 2–43 55
- Click Finish 56
- Altera Corporation 2–45 57
- DTW Limitations 58
- 2–48 Altera Corporation 60
- 3. Using the 61
- 3–2 Altera Corporation 62
- -dwz_file <value> 63
- -? or -help 63
- -after_iptb <value> 64
- -auto_adjust_cycles 64
- -extract_tcos <value> 64
- *auk_ddr_datapath 65
- *auk_qdrii_sram_datapath 65
- *auk_rldramii_datapath 65
- -stop_after <value> 66
- -vwf_file_name <value> 66
- -write_side 66
- Altera Corporation 3–7 67
- ■ Timing Summary 67
- Altera Corporation 3–9 69
- ■ Recommended Settings 69
- Timing Closure 72
- Altera Corporation 3–13 73
- Note to Figure 3–6: 73
- DDR2/DDR SDRAM Interfaces 74
- QDRII+/QDRII SRAM Interfaces 74
- RLDRAM II Interfaces 75
- 3–16 Altera Corporation 76
- Timing Closure Process 76
- Altera Corporation 3–17 77
- Analyzer 78
- Altera Corporation 3–19 79
- 3–20 Altera Corporation 80
- Altera Corporation 3–21 81
- 3–22 Altera Corporation 82
- Changing Clock Phase Shift 83
- 3–24 Altera Corporation 84
- Altera Corporation 3–25 85
- Changing Clock Cycles 87
- 3–28 Altera Corporation 88
- Altera Corporation 3–29 89
- 3–30 Altera Corporation 90
- ° phase shift in 90
- Altera Corporation 3–31 91
- Conclusion 92
Produits connexes et manuels pour Instruments de mesure Altera DDR Timing Wizard
Instruments de mesure Altera DSP Development Kit, Cyclone II Edition Getting St Manuel d'utilisateur
(32 pages)
(32 pages)
Instruments de mesure Altera DSP Development Kit, Stratix & Stratix Profess Manuel d'utilisateur
(26 pages)
(26 pages)
© 2020, manymanuals.fr. Tous droits réservés | 0.031 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Commentaires sur ces manuels