Altera I/O Buffer (ALTIOBUF) IP Core Manuel d'utilisateur

I/O Buffer (ALTIOBUF) IP Core User Guide2014.12.15UG-01024SubscribeSend FeedbackThe ALTIOBUF megafunction IP core implements either an I/O input buffe

Table 3: ALTIOBUF Parameters: Dynamic Delay Chains TabParameter DescriptionEnable input buffer dynamic delay chain If enabled, the input or bidirectio

ALTIOBUF Input, Output, and OE PathsThe three path types used with the I/O buffer in the delay chain architecture are input path, output path,and oe p

Figure 7: Internal Architecture of ALTIOBUF (Input Buffer Mode)This figure shows the internal architecture of the input buffer in the ALTIOBUF IP core

Figure 9: ALTIOBUF (Output Buffer Mode) Connected with the External FlipflopsThis figure shows how to connect the output and oe registers to the ALTIO

By following these specifications, only the input path needs a register external to the IP core. The outputand oe registers that are added externally

Figure 13: Output BufferThis figure shows an example of an output buffer.ioconfiga_0obufa_0output_dyn_delay_chain1a_0oe_dyn_delay_chain1a_0output_dyn_

ALTIOBUF ReferencesProvides the signals, parameters, Verilog HDL prototype, and VHDL component declaration forALTIOBUF IP core.Related InformationUsin

Name Required Descriptionio_config_clkena[] No Input clock-enable that feeds the ena port of IO_CONFIG foruser-driven dynamic delay chain.Input port [

Table 8: ALTIOBUF (As Input Buffer) ParametersThis table lists the parameters for the ALTIOBUF IP core (as input buffer).Name Required Type Descriptio

Table 9: ALTIOBUF (As Output Buffer) Input PortsThis table lists the input ports for the ALTIOBUF IP core (as output buffer).Name Required Description

buffers, you can connect these ports to the ALTOCT IP core to enable dynamic calibration for on-chiptermination.The additional dynamic termination con

Name Required Descriptionio_config_update No Input port that feeds the IO_CONFIG update portfor user-driven dynamic delay chain. Whenasserted, the ser

Name Required Descriptionparallelterminationcontrol_b No Receives the current state of the pull up and pulldown Rt control buses from a termination lo

Name Required Type DescriptionUSE_DIFFERENTIAL_MODE No String Specifies whether the output buffermode is differential. Values are TRUEand FALSE. When

Name Required Type DescriptionNUMBER_OF_CHANNELS Yes Integer Specifies the number of I/O buffersthat must be instantiated. Value mustbe greater than o

Name Required Descriptionio_config_clk No Input clock port that feeds the IO_CONFIG for user-driven dynamic delay chain. The maximumfrequency for this

Name Required Descriptiondynamicterminationcontrol[] NoInput signal for bidirectional I/Os. Input port[NUMBER_OF_CHANNELS - 1..0] wide. Whenspecified,

Name Required Descriptionparallelterminationcontrol_b No Receives the current state of the pull up and pulldown Rt control buses from a termination lo

Name Required Type DescriptionUSE_ DIFFERENTIAL_MODE No String Specifies whether the bidirectional bufferis differential. Values are TRUE and FALSE.Wh

Name Required Type DescriptionUSE_OUT_DYNAMIC_DELAY_CHAIN1 No String Specifies whether the output bufferincorporates a user-driven dynamic delaychain

VHDL LIBRARY-USE DeclarationThe VHDL LIBRARY-USE declaration is not required if you use the VHDL Component Declaration.LIBRARY altera_mf;USE altera_mf

of the deskew delay chains is only designed to compensate for a reasonable amount of board and package/layout skew.Related InformationALTOCT IP Core U

Date Version ChangesNovember 2007 1.0 Initial Release.30Document Revision HistoryUG-010242014.12.15Altera CorporationI/O Buffer (ALTIOBUF) IP Core Use

Use the following features to help you quickly locate and select an IP core:• Filter IP Catalog to Show IP for active device family or Show IP for all

Figure 4: IP Parameter EditorsView IP portand parameter detailsApply preset parameters forspecific applicationsSpecify your IP variation nameand targe

for synthesis and simulation. Some IP cores also simultaneously generate a testbench or exampledesign for hardware testing.5. To generate a simulation

Before you begin• Archive the Quartus II project containing outdated IP cores in the original version of the Quartus IIsoftware: Click Project > Ar

• To simultaneously upgrade multiple IP cores that support auto-upgrade, type the followingcommand:quartus_sh –ip_upgrade –variation_files “<my_ip_

Parameter DescriptionUse dynamic termination control(s) If enabled, this port receives the command to select either Rscode (when input value = low) or