Altera DDR Timing Wizard Manuel d'utilisateur Page 3
- Page / 92
- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Altera Corporation iii
November 2007
Table of Contents
About this User Guide .............................................................................. v
Revision History .................................................................................................................................... 1–v
How to Contact Altera .......................................................................................................................... 1–v
Typographic Conventions .................................................................................................................. 1–vi
Chapter 1. About the DDR Timing Wizard
Release Information ............................................................................................................................... 1–1
Device Family Support ......................................................................................................................... 1–2
Introduction ............................................................................................................................................ 1–2
Background ....................................................................................................................................... 1–2
DDR Timing Wizard ........................................................................................................................ 1–3
Features ................................................................................................................................................... 1–6
Chapter 2. Getting Started
System and Software Requirements ................................................................................................... 2–1
Design Flow ............................................................................................................................................ 2–1
Launching the DDR Timing Wizard ................................................................................................... 2–5
Entering and Editing Inputs to the DTW ........................................................................................... 2–6
Import Flow for the Altera Legacy Memory Controller IP Core or Recommended Data Path
.............................................................................................................................................................. 2–7
Manual Flow for Other External Memory Interfaces or Source Synchronous Systems ...... 2–14
The DTW Pages for DDR/DDR2 SDRAM ............................................................................ 2–14
The DTW Pages for QDRII+/QDRII SRAM & RLDRAM II ............................................... 2–45
DTW Limitations ................................................................................................................................. 2–46
Chapter 3. Using the dtw_timing_analysis.tcl Script
Introduction ............................................................................................................................................ 3–1
Running dtw_timing_analysis.tcl Script ....................................................................................... 3–3
The dtw_timing_analysis.tcl Script Results .................................................................................. 3–6
Timing Closure Process ...................................................................................................................... 3–12
Timing Closure Differences in DDR2/DDR SDRAM, QDRII+/QDRII SRAM, and RLDRAM II
Interfaces .......................................................................................................................................... 3–14
DDR2/DDR SDRAM Interfaces ............................................................................................. 3–14
QDRII+/QDRII SRAM Interfaces ........................................................................................... 3–14
RLDRAM II Interfaces .............................................................................................................. 3–15
Selecting Initial Phase Shifts ......................................................................................................... 3–16
Re-run DTW After First Compile When Using Classic Timing Analyzer ............................. 3–18
Ensure the Changes Made Outside Legacy Controller MegaWizard Are Not Erased When the
Core is Regenerated ....................................................................................................................... 3–19
Decide When to Change Clock Phase Shift ................................................................................ 3–21
- DDR Timing Wizard 1
- Table of Contents 3
- November 2007 4
- About this User Guide 5
- Typographic 6
- Conventions 6
- 1. About the DDR Timing 7
- Device Family 8
- 1–4 Altera Corporation 10
- Introduction 10
- Altera Corporation 1–5 11
- About the DDR Timing Wizard 11
- Note to Figure 1–1: 11
- Features 12
- 2. Getting Started 13
- Design Flow 14
- 2–2 Altera Corporation 14
- Altera Corporation 2–3 15
- Getting Started 15
- 2–4 Altera Corporation 16
- Launching the 17
- DDR Timing 17
- Entering and 18
- Editing Inputs to 18
- Recommended Data Path 19
- 2–8 Altera Corporation 20
- Altera Corporation 2–9 21
- 2–10 Altera Corporation 22
- Altera Corporation 2–11 23
- 2–12 Altera Corporation 24
- Altera Corporation 2–13 25
- Synchronous Systems 26
- Altera Corporation 2–15 27
- (Figure 2–10) 28
- Altera Corporation 2–17 29
- 2–18 Altera Corporation 30
- Analysis & Synthesis 31
- 2–20 Altera Corporation 32
- Altera Corporation 2–21 33
- 2–22 Altera Corporation 34
- Click Next 35
- 2–24 Altera Corporation 36
- Altera Corporation 2–25 37
- 2–26 Altera Corporation 38
- Altera Corporation 2–27 39
- 2–28 Altera Corporation 40
- Altera Corporation 2–29 41
- Altera Corporation 2–31 43
- 200 MHz) 44
- Altera Corporation 2–33 45
- 2–34 Altera Corporation 46
- Altera Corporation 2–35 47
- 2–36 Altera Corporation 48
- Altera Corporation 2–37 49
- 2–38 Altera Corporation 50
- Altera Corporation 2–39 51
- 2–40 Altera Corporation 52
- Altera Corporation 2–41 53
- 2–42 Altera Corporation 54
- Altera Corporation 2–43 55
- Click Finish 56
- Altera Corporation 2–45 57
- DTW Limitations 58
- 2–48 Altera Corporation 60
- 3. Using the 61
- 3–2 Altera Corporation 62
- -dwz_file <value> 63
- -? or -help 63
- -after_iptb <value> 64
- -auto_adjust_cycles 64
- -extract_tcos <value> 64
- *auk_ddr_datapath 65
- *auk_qdrii_sram_datapath 65
- *auk_rldramii_datapath 65
- -stop_after <value> 66
- -vwf_file_name <value> 66
- -write_side 66
- Altera Corporation 3–7 67
- ■ Timing Summary 67
- Altera Corporation 3–9 69
- ■ Recommended Settings 69
- Timing Closure 72
- Altera Corporation 3–13 73
- Note to Figure 3–6: 73
- DDR2/DDR SDRAM Interfaces 74
- QDRII+/QDRII SRAM Interfaces 74
- RLDRAM II Interfaces 75
- 3–16 Altera Corporation 76
- Timing Closure Process 76
- Altera Corporation 3–17 77
- Analyzer 78
- Altera Corporation 3–19 79
- 3–20 Altera Corporation 80
- Altera Corporation 3–21 81
- 3–22 Altera Corporation 82
- Changing Clock Phase Shift 83
- 3–24 Altera Corporation 84
- Altera Corporation 3–25 85
- Changing Clock Cycles 87
- 3–28 Altera Corporation 88
- Altera Corporation 3–29 89
- 3–30 Altera Corporation 90
- ° phase shift in 90
- Altera Corporation 3–31 91
- Conclusion 92
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